Trench Gate Structures for Power Semiconductor Loss Reduction
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Solution Overview
Problem
Power semiconductor devices face challenges with high on-state losses, hole drainage, unstable gate parameters, and reduced blocking capability, particularly in trench MOS cell designs, which compromise controllability and efficiency.
Innovation Solution
A semiconductor device with a specific layer structure and trench gate architecture, featuring a drift layer, multiple base layers, and trench gate structures angled between 45 to 90 degrees, allowing for reduced trench mesa dimensions and improved carrier storage, while controlling input capacitance through floating or grounded gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If trench gate structures are used to improve carrier storage and reduce on-state losses, then conduction losses are reduced, but blocking capability deteriorates due to high peak electric fields near trench corners
Solution Approach 1:
The patent applies local quality by creating different trench structures in different regions: main trenches with optimized dimensions for carrier storage in active regions, and dummy trenches with different dimensions in non-active regions to reduce peak electric fields. This local differentiation allows each region to be optimized for its specific function, resolving the contradiction between conduction losses and blocking capability.
Solution Approach 2:
The gate structure is segmented into multiple independent trenches (main trenches and dummy trenches) rather than a single continuous structure. This segmentation allows independent optimization of each trench's dimensions and positioning, enabling the system to simultaneously achieve good carrier storage in main trenches and reduced peak fields through strategically placed dummy trenches.
2Loss of energy
If trench gate structures are used to improve carrier storage, then on-state losses are reduced, but gate parameter stability deteriorates due to hot carrier injection into gate oxide
Solution Approach 1:
Dummy trenches are strategically placed in non-active regions where they create localized electric field modifications without interfering with the main carrier storage function. This local quality adjustment reduces peak electric fields that cause hot carrier injection, thereby stabilizing gate parameters while preserving the low on-state losses achieved through main trench structures.
3Loss of energy
If trench gate structures are used to improve carrier storage, then conduction losses are reduced, but device controllability deteriorates due to large MOS accumulation region and associated capacitance
Solution Approach 1:
The gate structure is divided into main trenches for carrier storage and separate dummy trenches for electric field control. This segmentation allows the dummy trenches to be positioned and dimensioned specifically to reduce accumulation region effects without compromising the main trenches' carrier storage capability, thereby improving controllability while maintaining low conduction losses.
4Loss of energy
If high cell density is used to reduce channel resistance, then channel resistance is reduced, but short circuit currents increase
Solution Approach 1:
The patent uses local quality by placing dummy trenches specifically in non-active regions between cells. This creates localized electric field modifications that affect hole drainage and short circuit current behavior in specific areas, allowing high cell density for low channel resistance while using dummy trenches to mitigate the harmful short circuit current effects in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves reduced on-state losses, enhanced blocking capability, stable gate parameters, and improved controllability, enabling high-density trench patterns and narrow mesa designs, suitable for both IGBTs and MOSFETs, including those based on silicon and wide bandgap materials.
Implementation Method 1
the trench gate electrode (11) which offers a vertical MOS channel (16) for enhanced injection of electrons in the vertical direction
Implementation Method 2
The main gate electrodes are electrically insulated from the emitter electrode by a first insulation layer, and from the source region, the first base layer, and the drift layer by an insulating gate oxide
Data Source
AI summary
A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.