Trench Gate Pull-Up Insulation for Gate Oxide Breakdown Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with trench-type insulated gate structures face challenges in preventing breakdown of the gate insulating film due to high electric fields and high dV/dt rates, particularly at the trench shoulder portion, leading to potential insulating film breakdown.
Innovation Solution
A semiconductor device design where the trench shoulder, sidewall, and bottom portions in the gate pull-up region are covered with a field insulating film thicker than the gate insulating film, with the gate lead-out wiring line formed on this field insulating film, ensuring the thickness of the insulating film covering these areas is equivalent to or greater than that under the gate pad, thereby alleviating electric field concentration and preventing breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate insulating film is increased in the gate pull-up portion to prevent breakdown, then the resistance to electric field concentration is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by forming a field insulating film with greater thickness specifically in the gate pull-up portion where the trench shoulder is located, while maintaining a different insulating film structure in other regions. This localized thickening addresses the electric field concentration problem at the critical trench shoulder area without unnecessarily increasing insulation thickness throughout the entire device, thereby improving breakdown resistance at the vulnerable location while controlling overall device complexity.
2Reliability
If the radius of curvature of the trench shoulder portion is increased to prevent electric field concentration, then the breakdown resistance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by modifying the thickness parameter of the field insulating film in the gate pull-up portion rather than changing the geometric curvature parameter of the trench shoulder. This approach transitions from controlling the shape parameter (radius of curvature) to controlling the material parameter (insulating film thickness), which is easier to manufacture with standard semiconductor fabrication processes while achieving the same goal of reducing electric field concentration and preventing breakdown.
3Power
If a wide band gap semiconductor such as silicon carbide is used to achieve high withstand voltage and high speed operation, then the power handling capability is improved, but the displacement current increases causing potential breakdown of the field insulating film under the gate pad
Solution Approach 1:
The patent applies beforehand cushioning by forming a field insulating film with greater thickness in advance in the gate pull-up portion and under the gate pad, before the high voltage switching operation occurs. This pre-formed thick insulating film acts as a cushion or protective barrier that can withstand the displacement current generated during high dV/dt switching operations of wide band gap semiconductors, preventing breakdown while allowing high power operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly enhances the resistance to insulating film breakdown when a gate voltage is applied and during high dV/dt switching, effectively preventing film breakdown and maintaining device reliability.
Implementation Method 1
Since an electric field is concentrated in a trench shoulder portion of the gate pull-up portion when a voltage is applied to the gate electrode, the breakdown of the gate insulating film is likely to occur at that portion
Data Source
AI summary
A semiconductor device includes a trench formed in a semiconductor layer of an active region, a gate insulating film and a gate electrode formed in the trench, a gate pad formed on a field insulating film, and a gate lead-out wiring line connecting the gate pad and the gate electrode. A shoulder portion, a sidewall portion, and a bottom portion of the trench are covered with the field insulating film in a gate pull-up portion which is an end portion of the trench corresponding to a place where the gate lead-out wiring line and the gate electrode in the trench are connected. The thickness of the field insulating film covering the shoulder portion, the sidewall portion, and the bottom portion of the trench in the gate pull-up portion is equivalent to or larger than the thickness of the field insulating film under the gate pad.