Trench Gate Resistance Layout for Breakdown-Safe Semiconductors
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Solution Overview
Problem
Existing semiconductor devices with integrated gate resistive circuits face manufacturing complexity and increased area due to separate processes for trench gate structures and polysilicon resistors, leading to potential breakdowns in the gate resistance region.
Innovation Solution
A semiconductor device design incorporating a first semiconductor region with a gate electrode via a first insulating film, a second semiconductor region with a gate resistance region having a second trench structure via a second insulating film, where the depth of the third semiconductor region is deeper than the second semiconductor region but shallower than the trench depth, allowing for simultaneous formation of gate and gate resistance trench structures to reduce manufacturing variations and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon resistor is formed via an insulating film on the semiconductor substrate surface in a separate process from the trench gate structure, then the gate resistance function is achieved, but the manufacturing process complexity increases and the semiconductor device area increases
Solution Approach 1:
The patent merges the gate electrode trench structure and the gate resistance trench structure into a single integrated trench configuration. The gate electrode is formed in a first trench region while the gate resistance is formed in a second trench region that is electrically connected to the first trench region, allowing both functions to be achieved in one manufacturing process rather than separate processes.
Solution Approach 2:
The trench structure serves multiple functions simultaneously: it provides the gate electrode formation region, the gate resistance formation region, and the electrical connection between them. This multi-functional design eliminates the need for separate polysilicon resistor formation processes while maintaining both gate control and resistance functions.
2Reliability
If a polysilicon resistor is formed via an insulating film on the semiconductor substrate surface, then the gate resistance function is achieved, but the semiconductor device area increases
Solution Approach 1:
The gate resistance trench structure is nested within the overall gate structure, with the second trench region positioned adjacent to and electrically connected with the first trench region. This nested arrangement allows the gate resistance to be formed within the gate structure footprint rather than requiring separate area on the semiconductor substrate surface.
3Area of stationary object
If a trench structure is used for the polysilicon resistor, then the area is reduced, but breakdown may occur in the gate resistance region
Solution Approach 1:
The patent applies different structural characteristics to different regions: the first trench region containing the gate electrode has one configuration while the second trench region containing the gate resistance has a different configuration optimized for resistance function. The third semiconductor region is positioned at a specific depth between the second semiconductor region and the gate resistance trench bottom, providing localized electrical field control to prevent breakdown in the gate resistance region.
4Adaptability or versatility
If separate processes are used for trench gate structure and polysilicon resistor formation, then each structure can be optimized independently, but manufacturing variations increase
Solution Approach 1:
By combining the gate electrode and gate resistance formation into a single trench structure formed in one process, the patent eliminates manufacturing variations that would arise from aligning separate processes. The first and second trench regions are formed simultaneously, ensuring consistent spacing, depth, and electrical connection without the need for separate alignment steps.
Data Source
AI summary
The semiconductor device according to one or more embodiments includes a first semiconductor region of a first conductivity type, a second semiconductor region of the second conductivity type formed on the first semiconductor region, and a semiconductor region containing a first trench structure in which a gate electrode is formed via an insulating film on the second semiconductor region, a third semiconductor region of the second conductivity type provided electrically connected to the second semiconductor region in a planar view, and a gate resistance region including a second trench structure in which a gate resistor is formed via an insulating film on the third semiconductor region. The depth of the third semiconductor region is deeper than the depth of the second semiconductor region and shallower than the trench depth of the second trench structure.