Trench Gate Semiconductor Structure for Lower Saturation Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with trench gate structures face increased costs and complex processes to achieve a small saturation current value, leading to high on-resistance and compromised electrical characteristics.
Innovation Solution
Incorporating low-concentration regions with impurity concentrations lower than the n+-type source regions, which reduce the pinch-off voltage and saturation current value, while maintaining acceptable electrical characteristics and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional structures with trench gate structures are used to achieve small saturation current value, then saturation current value is reduced, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent changes the impurity concentration parameter by introducing a low-concentration region with impurity concentration lower than the n+-type source region. This parameter change enables the formation of a depletion layer that extends toward the drain region, facilitating channel pinching-off and reducing saturation current value without requiring complex trench gate structures
Solution Approach 2:
The patent applies local quality by creating a specific low-concentration region only in the area where channel pinching-off is needed. The impurity concentration is locally reduced in the low-concentration region while other regions maintain their original doping levels, enabling targeted control of the depletion layer formation and channel cutoff without affecting the entire device structure
2Reliability
If conventional structures are used to reduce saturation current value, then saturation current value is reduced, but on-resistance increases
Solution Approach 1:
The patent optimizes the impurity concentration parameter in the low-concentration region to achieve a balance between saturation current reduction and on-resistance control. By carefully selecting the impurity concentration level and the dimensions of the low-concentration region, the patent enables effective channel pinching-off while maintaining low on-resistance through proper depletion layer management
Solution Approach 2:
The patent applies local quality by confining the low-concentration region to specific areas where channel control is needed, while other regions maintain higher impurity concentrations to ensure low on-resistance. This spatial differentiation of impurity concentrations allows simultaneous optimization of both saturation current and on-resistance characteristics
3Reliability
If conventional structures are used to achieve small saturation current value, then saturation current value is reduced, but manufacturing cost increases
Solution Approach 1:
The patent changes the impurity concentration parameter to create a low-concentration region that can be formed using standard semiconductor manufacturing techniques such as ion implantation or diffusion processes. This parameter change achieves saturation current reduction without requiring expensive or complex additional manufacturing steps
Solution Approach 2:
The patent applies local quality by creating a low-concentration region in specific areas using conventional doping techniques. The low-concentration region is formed by localized ion implantation or diffusion, which are standard manufacturing processes, thereby achieving saturation current reduction without significantly increasing manufacturing cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves improved short-circuit withstand capability with reduced saturation current value and on-resistance, while maintaining electrical characteristics and reducing manufacturing complexity and costs.
Implementation Method 1
a p−-type low-concentration region having a p-type impurity concentration that is lower than that of the p-type base region is disposed, thereby, facilitating the pinching-off of channels
Implementation Method 2
when voltage (forward voltage) that is positive with respect to a source electrode is applied to a drain electrode, depletion of the JFET region is facilitated, whereby the saturation current value becomes smaller
Data Source
AI summary
N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n−-type or a p−-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.