Trench Semiconductor Gate Electrode Segmentation for Avalanche Ruggedness
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Solution Overview
Problem
Trench type semiconductor devices face challenges in achieving optimal avalanche ruggedness and performance metrics such as on-state resistance and breakdown voltage, particularly due to constraints in silicon mesa width and susceptibility to repetitive avalanche cycles.
Innovation Solution
The semiconductor device incorporates a trench structure with a source trench and a gate trench, featuring a shield electrode and a buried electrode, respectively, which enables charge balancing and two-dimensional depletion of the drift region, allowing for reduced mesa width and enhanced avalanche current diversion, thereby improving ruggedness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the silicon mesa is reduced to increase doping concentration, then on-state resistance is improved, but the device becomes more susceptible to avalanche damage and parametric shifts
Solution Approach 1:
The gate structure is segmented into two distinct electrodes: a gate electrode positioned in the upper portion of the gate trench and a buried electrode positioned in the lower portion. This segmentation allows independent optimization of each electrode's function, enabling the buried electrode to provide avalanche protection while the gate electrode controls device operation, thus improving avalanche ruggedness without requiring increased mesa width
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a vertical stacked configuration with the gate electrode above the buried electrode. This dimensional change allows the electrodes to be positioned at different depths within the gate trench, creating separate functional zones that can independently address on-state resistance and avalanche ruggedness requirements
2Reliability
If the cell pitch is reduced to lower on-state resistance, then device performance is improved, but the silicon mesa width becomes too narrow for adequate contact metallization fill
Solution Approach 1:
By segmenting the gate into upper and lower electrodes with distinct functions, the invention enables independent optimization of the contact structure. The buried electrode can extend to provide robust electrical connection without compromising the silicon mesa width, as its function is separated from the gate control function, thereby maintaining adequate contact opening dimensions for reliable metallization fill
Solution Approach 2:
The buried electrode acts as an intermediary structure that provides electrical connection between the gate trench and the drift region. This intermediary element enables current flow without requiring narrow contact openings, as it establishes a direct conduction path that bypasses the need for narrow surface contacts, thus resolving the conflict between cell pitch reduction and manufacturability
3Reliability
If the doping concentration of the drift region is increased to reduce on-state resistance, then device performance is improved, but breakdown voltage decreases
Solution Approach 1:
The segmented gate structure with upper and lower electrodes enables independent control of different functional regions. The buried electrode in the lower portion can be configured to maintain high breakdown voltage by creating an extended depletion region, while the upper gate electrode controls the channel for low on-state resistance, thus resolving the trade-off between these two parameters
Solution Approach 2:
The invention changes the electrical parameters of different regions through the dual-electrode configuration. The buried electrode modifies the electric field distribution in the lower drift region to maintain high breakdown voltage, while the gate electrode optimizes the channel characteristics for low on-state resistance, effectively decoupling these two parameters through spatial parameter variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the risk of parametric shifts and enhances avalanche ruggedness by evenly distributing high electric fields and avalanche current, minimizing damage from avalanche conditions and allowing for higher doping concentrations for lower on-state resistance.
Implementation Method 1
gate trench dielectrics 212 that line sidewalls 214 and bottom 216 of gate trench 210 and electrically isolate gate electrode 220 from buried electrode 218
Implementation Method 2
The breakdown voltage is the voltage at which a reverse biased drift-base p-n junction breaks down and significant current starts to flow between a source and a drain of the trench type semiconductor device by an avalanche multiplication process. In the avalanche multiplication process, impact ionization of electron-hole pairs can generate avalanche current between the drain and a base region of the semiconductor device.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.