Trench Gate Semiconductor Device for Driving Current
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Solution Overview
Problem
As semiconductor devices are scaled to 130 nm or less, conventional methods to improve driving current, such as shortening the gate length or increasing gate oxide capacitance, become ineffective, and increasing gate dimension in the channel width direction leads to larger chip areas, hindering scaling down processes.
Innovation Solution
The semiconductor device features a substrate with isolation and active regions, where trenches are formed in the active region, and a gate layer is conformably filled within these trenches, extending in a different direction to increase gate width without expanding the chip size, using insulating and conductive materials like SiO2 and metal or silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate dimension in the channel width direction is increased to improve driving current, then the driving current increases, but the chip area occupied by the gate increases
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional trench gate structure. By etching trenches into the substrate and filling them with gate material, the gate extends vertically into the substrate, effectively utilizing the third dimension (depth) to increase gate width without expanding the horizontal chip footprint. This dimensional transition resolves the contradiction between improving driving current and maintaining compact chip area.
Solution Approach 2:
The gate structure is nested within the substrate by forming trenches and filling them with gate material. The gate layer is embedded inside the substrate volume, similar to nested dolls, allowing the gate to occupy space within the existing chip volume rather than requiring additional surface area. This nesting approach enables increased gate width while maintaining the original chip dimensions.
2Length of moving object
If conventional scaling methods are used at 130 nm or less, then device size is reduced, but driving current improvement becomes difficult
Solution Approach 1:
At scaled dimensions of 130 nm or less, the patent introduces vertical trench gates that extend into the substrate depth, compensating for the reduced horizontal dimensions. This three-dimensional approach allows continued device scaling while maintaining or improving driving current through increased effective gate width in the vertical dimension, overcoming the limitations of conventional planar scaling.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure by transitioning from a two-dimensional planar gate to a three-dimensional trench gate with specific depth and width parameters. By optimizing the trench depth, width, and filling material properties, the effective gate width is increased without proportionally reducing other critical dimensions, thereby improving driving current even as overall device size is scaled down.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device.