Trench Gate Semiconductor Device Impurity Distribution
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Solution Overview
Problem
Conventional semiconductor devices with trench gate structures face challenges in suppressing the increase in capacitance between the drain and source while improving breakdown voltage due to the configuration of the p/n interface and overlapping p-type semiconductor regions.
Innovation Solution
A semiconductor device with a trench gate structure is designed, featuring a p-type impurity-containing region that does not overlap with the source electrode, an insulating film covering the trench, and specific impurity concentration gradients to reduce capacitance and enhance breakdown voltage, including a p-type impurity region with higher concentration at the trench's outer periphery and a second n-type semiconductor region with lower impurity concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a p-type semiconductor region is arranged to entirely overlap with the source electrode in the stacking direction, then the breakdown voltage is improved, but the capacitance between drain and source increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform p-type impurity concentration distribution within the p-type semiconductor layer. Specifically, the p-type impurity concentration is made higher in regions adjacent to the trench gate structure and lower in regions overlapping with the source electrode. This localized variation in impurity concentration allows the device to achieve high breakdown voltage near the trench while reducing capacitance in regions overlapping with the source electrode, thus resolving the technical contradiction between these two parameters.
2Strength
If a p/n interface is located below the trench, then the breakdown voltage is improved, but the capacitance between drain and source increases
Solution Approach 1:
The patent positions the p/n interface below the trench gate structure to enhance breakdown voltage, as this location provides better electric field distribution. However, to prevent capacitance increase, the patent combines this with a non-uniform impurity concentration profile where the p-type region has lower concentration in areas overlapping with the source electrode, thus achieving both high breakdown voltage and low capacitance.
3Strength
If the p-type impurity concentration is increased to improve breakdown voltage, then the breakdown voltage is improved, but the on-resistance increases
Solution Approach 1:
The patent resolves this contradiction by implementing spatially varying p-type impurity concentrations. High p-type impurity concentration is localized in regions adjacent to the trench gate where high breakdown voltage is critical, while lower p-type impurity concentration is used in regions overlapping with the source electrode where low on-resistance is more important. This local differentiation allows simultaneous optimization of both breakdown voltage and on-resistance.
Solution Approach 2:
The patent introduces a vertical dimension to the impurity concentration profile by creating depth-dependent concentration variations. The p-type impurity concentration varies not only laterally but also vertically through the p-type semiconductor layer, with different concentration levels at different depths. This three-dimensional concentration control enables independent optimization of breakdown voltage (affected by peak concentration near trench) and on-resistance (affected by average concentration in current flow paths).
Data Source
AI summary
A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.