Trench Gate Semiconductor Device Impurity Profile Control
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Solution Overview
Problem
Existing semiconductor device manufacturing methods face challenges in achieving miniaturization while maintaining low on-state voltage, preventing threshold voltage and on-state voltage rises, and ensuring high breakdown resistance, due to variations in mask patterns and processing steps.
Innovation Solution
A semiconductor device manufacturing method involving a trench gate structure with specific impurity concentration profiles and ion implantation steps to form alternating regions, ensuring precise placement and depth of n+-type emitter and p++-type contact regions, and the introduction of a p+-type region to maintain channel width and prevent encroachment, thereby stabilizing the impurity concentrations and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the mesa portion is miniaturized by disposing trenches at a short pitch, then the IE effect is increased and on-state voltage is reduced, but the threshold voltage rises and breakdown resistance decreases
Solution Approach 1:
The patent applies local quality by creating a p+-type region with higher impurity concentration specifically in the channel portion adjacent to the p++-type contact region, while maintaining lower impurity concentration in other areas. This localized impurity concentration adjustment prevents threshold voltage rise without compromising the overall miniaturization benefits and IE effect.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a p+-type region with impurity concentration higher than the p−-type base region but lower than the p++-type contact region. This parameter adjustment stabilizes the channel characteristics, preventing threshold voltage rise while maintaining the miniaturized structure's low on-state voltage performance.
2Loss of energy
If the p++-type contact region is disposed in a linear planar layout extending in the first direction in a central portion of the mesa portion, then the IE effect is increased, but the threshold voltage rises due to encroachment into the channel portion
Solution Approach 1:
The patent introduces a p+-type region with intermediate impurity concentration between the p−-type base region and p++-type contact region. This creates a gradual transition zone that prevents the high-concentration p++-type contact region from encroaching into the channel portion, thereby maintaining precise channel width control while preserving the IE effect benefits.
Solution Approach 2:
The p+-type region acts as an intermediary layer between the p−-type base region and the p++-type contact region. This intermediate region with moderate impurity concentration prevents direct encroachment of the high-concentration contact region into the channel, maintaining manufacturing precision while allowing the contact region to be positioned for optimal IE effect.
3Productivity
If process variations occur in mask pattern intervals, then the intervals between emitter regions and contact regions vary, but with existing structures this causes threshold voltage and on-state voltage to rise or breakdown resistance to decrease
Solution Approach 1:
The patent applies beforehand cushioning by introducing a p+-type region with intermediate impurity concentration that acts as a buffer zone. This cushioning structure compensates for process variations in mask pattern intervals, preventing threshold voltage and on-state voltage from rising or breakdown resistance from decreasing, thereby improving process tolerance while maintaining voltage stability.
Solution Approach 2:
The patent changes the impurity concentration parameter by creating a p+-type region with intermediate concentration between the p−-type base region and p++-type contact region. This parameter adjustment creates a more robust structure that is less sensitive to process variations, maintaining stable threshold voltage and on-state voltage even when mask pattern intervals vary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for miniaturization of trench gate semiconductor devices with stable on-state voltage, threshold voltage, and breakdown resistance, maintaining a good trade-off between on-state voltage and switching loss, even with process variations.
Implementation Method 1
A semiconductor device manufacturing method involving a trench gate structure with specific impurity concentration profiles and ion implantation steps to form alternating regions
Implementation Method 2
ensuring precise placement and depth of n+-type emitter and p++-type contact regions, and the introduction of a p+-type region to maintain channel width and prevent encroachment
Data Source
AI summary
A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N+-type emitter region and p++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates. P+-type region covers an end portion on lower side of junction interface between n+-type emitter region and p++-type contact region. Formation of trench gate structure is such that n+-type emitter region is selectively formed at predetermined intervals in the first direction in the mesa portion by first ion implantation. P+-type region is formed less deeply than n+-type emitter region in the entire mesa portion by second ion implantation. The p++-type contact region is selectively formed inside the p+-type region by third ion implantation. N+-type emitter region and p++-type contact region are diffused and brought into contact.