Trench Gate Semiconductor Device with Lateral Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power semiconductor devices face challenges with high on-state losses, unstable behavior during transitions, and large parasitic capacitances due to dense trench gate designs, which limit their electrical performance and controllability.
Innovation Solution
A semiconductor device design featuring multiple transistor cells with a highly doped second base layer and a unique MOS channel formation on lateral trench walls, eliminating the vertical trench channel and optimizing trench spacing for reduced losses and improved blocking capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high density of trench gates is used to achieve very low conduction losses, then the conduction losses are reduced, but large parasitic capacitances and unstable behavior during transitions occur
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions: a highly doped region at the trench gate interface and a lightly doped drift region elsewhere. This localized doping optimization allows the trench gate to provide strong carrier blocking (reducing conduction losses) while the overall device structure maintains stable transition behavior through controlled charge distribution.
Solution Approach 2:
The patent changes the doping concentration parameter spatially, with a first doping concentration in the drift region and a higher second doping concentration in the highly doped region adjacent to the trench gate. This parameter variation enables the device to achieve low conduction losses through efficient carrier control at the gate interface while maintaining stability during switching transitions through controlled charge storage in the drift region.
2Length of moving object
If the length of source regions in contact with trenches is increased to achieve the required total channel length, then the channel length is sufficient, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional structure where the channel forms along the lateral walls of the trench recesses. This dimensional change allows the effective channel length to be determined by the trench depth and lateral wall geometry rather than requiring long source region extensions, simplifying the manufacturing process while achieving the required total channel length at chip level.
Solution Approach 2:
Instead of extending source regions horizontally to increase channel length, the patent inverts the approach by forming the channel vertically along the trench walls. The channel length is now defined by the trench structure geometry rather than source region length, reversing the traditional design paradigm and enabling easier manufacturing with standard trench processing techniques.
3Reliability
If closely packed trenches are used to provide strong barrier to hole drainage, then reverse bias blocking performance is improved, but large parasitic capacitances occur
Solution Approach 1:
The patent applies local quality by concentrating high doping in specific regions adjacent to the trench gates rather than uniformly throughout the drift region. This localized doping provides strong hole drainage barriers where needed (improving reverse bias blocking) while minimizing the total doped volume, thereby reducing parasitic capacitances associated with extensive doped regions.
Solution Approach 2:
The patent creates a composite doping structure with regions of different doping concentrations: a highly doped region near the trench gate for effective hole blocking and a lightly doped drift region for low capacitance. This composite structure combines the benefits of strong reverse bias blocking with minimized parasitic capacitance, resolving the contradiction between these two parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced on-state losses, stable gate parameters, and enhanced controllability with improved blocking performance, suitable for both vertical and lateral IGBTs and MOSFETs, including those using silicon or wide bandgap materials.
Implementation Method 1
an inversion layer formed on the side walls of the trench recesses embedding the trench gate electrodes. The electrons will flow from the edge of the n source region along the side walls of adjacent trench recesses
Implementation Method 2
a vertical MOS channel is formed along the lateral walls of the trench recesses embedding the second gate electrodes. These MOS channels provide an unobstructed flow path for electrons from the source regions to the drift layer
Implementation Method 3
the vertical MOS channel is preventing from forming by an additional highly doped second p-base layer
Implementation Method 4
when a suitable control or gate voltage is applied on the trench gate electrodes, which are electrically interconnected, a vertical MOS channel is formed along the lateral walls of the trench recesses
Data Source
AI summary
A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.