Trench Gate Semiconductor Device Reducing Dynamic Resistance
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Solution Overview
Problem
Conventional semiconductor devices with inversion layers, such as MOSFETs, have high dynamic resistance due to thin channel thickness and low carrier mobility, which cannot be effectively reduced without increasing device size and manufacturing costs.
Innovation Solution
A semiconductor device with a trench gate structure where the gate electrode is buried in a trench via a gate insulating film, allowing for a thicker channel region and reduced dynamic resistance without increasing device size, by using a channel region that is fully depleted when off and conductive when on, without relying on an inversion layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the physical thickness of the channel is increased to reduce dynamic resistance, then the carrier mobility improves, but the device size increases
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional trench gate structure. The channel region is formed within a vertically extended trench, allowing the channel thickness to be controlled in the vertical dimension while maintaining a compact planar footprint. This dimensional transition enables independent optimization of channel thickness without proportionally increasing device area.
Solution Approach 2:
The gate electrode is nested within the trench structure, with the channel region positioned between the gate electrode and the semiconductor substrate surface. This nested arrangement allows the channel to be confined within the trench volume, achieving a thick channel for low resistance while containing the structure within a compact spatial envelope.
2Reliability
If the width of the gate electrode is geometrically increased to reduce dynamic resistance, then the channel width increases, but the manufacturing cost increases
Solution Approach 1:
Instead of increasing gate width in the planar direction, the patent exploits the vertical dimension by forming a deep trench structure. The channel thickness is controlled by trench depth rather than gate electrode width, allowing resistance reduction without increasing the lateral dimensions that would drive up manufacturing costs.
3Adaptability or versatility
If an inversion layer is used as the channel, then the device can be formed with standard MOSFET structure, but the carrier mobility is lower than in ordinary silicon
Solution Approach 1:
The patent extracts the channel formation mechanism from the inversion layer approach. Instead of relying on field-induced inversion layers at the silicon-silicon dioxide interface, the invention uses a fully depleted semiconductor channel region formed within the trench, eliminating the mobility-degrading effects of the inversion layer while maintaining MOSFET structural compatibility.
Solution Approach 2:
The patent changes the electrical state of the channel from an inverted state (excess minority carriers) to a fully depleted state (depletion of majority carriers). This parameter change in the channel's electrical condition fundamentally improves carrier mobility by eliminating the scattering effects present in inversion layers, while the trench gate structure maintains compatibility with standard MOSFET fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device with low dynamic resistance, suppressed carrier mobility degradation, and miniaturized size, while maintaining high affinity with other semiconductor elements and easy integration into LSI circuits.
Implementation Method 1
when a positive potential is applied to the gate electrode, electrons that are minority carriers in the semiconductor substrate are attracted to the gate electrode, and an inversion layer to electrically connect between the source region and drain region is formed
Implementation Method 2
a depletion layer is formed in a manner expanding toward the channel region from the gate electrode due to a built-in potential between the gate electrode and the channel region
Data Source
AI summary
A semiconductor device of the present invention includes a semiconductor layer, a source region and a drain region formed in a surface of the semiconductor layer, both having a first conductivity type, a plurality of gate trenches each formed so as to extend across the source region and the drain region, in a plan view observed in a direction of a normal to the surface of the semiconductor layer, a channel region of a first conductivity type made of the semiconductor layer sandwiched by the gate trenches adjacent to each other, having a channel length along a direction extending from the drain region to the source region, and a gate electrode buried in the gate trench via a gate insulating film, and the channel region has a thickness in the plan view not more than two times a width of a depletion layer to be generated due to a built-in potential between the channel region and the gate electrode.