Trench Gate Semiconductor Device with Integrated Schottky Diode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench gate semiconductor devices with integrated Schottky diodes face challenges in controlling gate voltage during dead time, leading to forward voltage drops and reduced breakdown tolerance due to the Schottky diode's lower breakdown current capacity compared to MOS transistors.
Innovation Solution
The design incorporates a trench gate semiconductor device with a Schottky diode integrated in parallel to the MOS transistor, featuring p-type doped layers with varying impurity concentrations to enhance breakdown tolerance and reduce forward voltage drops by controlling the depletion layer formation, ensuring that breakdown occurs in the MOS transistor portion rather than the Schottky diode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a Schottky diode is integrated in parallel in the MOS transistor to reduce forward voltage drop during dead time, then forward voltage drop is reduced, but breakdown tolerance decreases due to lower breakdown current capacity
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the semiconductor structure. Specifically, it forms a first impurity region with a first impurity concentration and a second impurity region with a second impurity concentration that is higher than the first. This localized variation in impurity concentration allows the device to simultaneously achieve low forward voltage drop (through the Schottky diode region) and high breakdown tolerance (through the higher doped region that supports higher breakdown current).
Solution Approach 2:
The patent employs parameter changes by varying the impurity concentration parameter across different regions of the semiconductor device. The first impurity region has a lower impurity concentration optimized for Schottky diode operation with low forward voltage drop, while the second impurity region has a higher impurity concentration optimized for withstanding breakdown currents. This parameter variation resolves the contradiction between reducing forward voltage drop and maintaining breakdown tolerance.
2Device complexity
If the Schottky diode occupies a small area to integrate in the MOS transistor, then device integration is improved, but tolerable breakdown current is reduced
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatial variation of impurity concentration. The Schottky diode region maintains a smaller area for good integration, while a separate region with higher impurity concentration is created to handle breakdown currents. The higher doped region can withstand higher current densities, compensating for the limited area of the Schottky diode and enabling both high integration density and adequate breakdown current capacity.
Solution Approach 2:
The patent uses parameter changes by modifying the impurity concentration parameter in different spatial regions. The first impurity region with lower concentration supports the Schottky diode function, while the second impurity region with higher concentration provides enhanced current handling capability. This parameter differentiation allows the device to achieve both compact integration and sufficient breakdown current tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the tolerable breakdown current and reduces forward voltage drops, improving the overall efficiency and reliability of the trench gate semiconductor device by managing the depletion layer effectively across different voltage states.
Implementation Method 1
featuring p-type doped layers with varying impurity concentrations to enhance breakdown tolerance and reduce forward voltage drops by controlling the depletion layer formation
Implementation Method 2
ensuring that breakdown occurs in the MOS transistor portion rather than the Schottky diode
Data Source
AI summary
A trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region.