Trench Gate Semiconductor Device with Segmented P-Type Regions
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Solution Overview
Problem
Conventional semiconductor devices with p-type semiconductor regions formed using a single type of p-type impurities with a large diffusion coefficient struggle to achieve a T-shape configuration under the trench gate, leading to increased on-resistance and reduced withstand voltage due to isotropic spreading.
Innovation Solution
The use of two types of p-type impurities with different diffusion coefficients, where a first type with a larger coefficient forms a shallower region under the trench gate's edge and a second type with a smaller coefficient forms a deeper region, creating a T-shape configuration that suppresses lateral spreading and enhances both withstand voltage and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single type of p-type impurities with a relatively large diffusion coefficient is used to form the p-type semiconductor region, then the p-type semiconductor region can be formed at a shallower position under the bottom face of the trench gate along the lateral direction, but it spreads isotropically and spreads along the lateral direction unnecessarily at the deeper position, resulting in an increase in on-resistance
Solution Approach 1:
The p-type semiconductor region is segmented into two distinct regions: a first p-type semiconductor region containing a first type of p-type impurities with a relatively large diffusion coefficient, and a second p-type semiconductor region containing a second type of p-type impurities with a relatively small diffusion coefficient. This segmentation allows each region to perform its specific function: the first region spreads laterally to position under the edge of the trench gate bottom face, while the second region spreads vertically to deeper positions with suppressed lateral spreading, thereby achieving the desired T-shape configuration without unnecessary lateral spread that would increase on-resistance
Solution Approach 2:
Different types of p-type impurities are used in different spatial locations within the p-type semiconductor region. The first type of p-type impurities with large diffusion coefficient is used in the first p-type semiconductor region where lateral spreading is desired, while the second type of p-type impurities with small diffusion coefficient is used in the second p-type semiconductor region where vertical spreading with suppressed lateral spreading is needed. This local differentiation of material properties enables precise control over the spreading behavior in different regions
2Reliability
If a single type of p-type impurities with a relatively large diffusion coefficient is used to form the p-type semiconductor region, then the p-type semiconductor region can be formed to contact the bottom face of the trench gate, but it cannot achieve the T-shape configuration with suppressed lateral spreading at deeper positions, resulting in reduced withstand voltage
Solution Approach 1:
The p-type semiconductor region is divided into two segments with different impurity types and diffusion characteristics. The first p-type semiconductor region with large diffusion coefficient impurities forms the upper part that spreads laterally under the edge of the trench gate bottom face, while the second p-type semiconductor region with small diffusion coefficient impurities forms the lower part that extends vertically to deeper positions with minimal lateral spreading. This segmented structure creates the T-shape configuration necessary for effective electric field relaxation and high withstand voltage
Solution Approach 2:
The diffusion coefficient parameter is changed by using different types of p-type impurities in different regions. The first type of p-type impurities has a relatively large diffusion coefficient to enable lateral spreading at shallower positions, while the second type of p-type impurities has a relatively small diffusion coefficient to enable vertical spreading at deeper positions with suppressed lateral spreading. This parameter change enables the formation of the T-shape configuration that optimizes both withstand voltage and on-resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved withstand voltage and reduced on-resistance by controlling the spreading of the p-type semiconductor region, maintaining high voltage and low resistance characteristics.
Implementation Method 1
a first type of p-type impurities is irradiated through the opening and toward the trench. In the irradiating of the second type of p-type impurities, the second type of p-type impurities is irradiated through the opening and toward the trench
Implementation Method 2
a p-type semiconductor region that satisfies these conditions is formed by thermal diffusion of a single type of p-type impurities having a relatively large diffusion coefficient
Data Source
AI summary
A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.