Trench Gate Semiconductor Device with Segmented Well Region
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Solution Overview
Problem
Semiconductor devices face the challenge of balancing short circuit tolerance with increased ON resistance due to the tradeoff between impurity concentration in the well region and carrier mobility, where reducing impurity concentration suppresses short-circuit current but increases ON resistance.
Innovation Solution
A semiconductor device with a trench gate structure, including a gate trench, source region, well region, and multilayer region with specific impurity regions forming p-n junctions and Schottky junctions, which constriction the current path during short circuits and expand it in non-short circuit states, reducing Joule heat and maintaining low ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the well region is reduced to suppress short-circuit current, then the short circuit tolerance is improved, but the ON resistance increases due to decreased carrier mobility
Solution Approach 1:
The well region is divided into multiple impurity concentration zones (first well region with higher impurity concentration near the source, second well region with lower impurity concentration near the drain). This segmentation allows different portions of the well region to serve different functions: the first well region maintains low ON resistance by providing high carrier concentration near the source, while the second well region suppresses short-circuit current by reducing impurity concentration near the drain.
Solution Approach 2:
Different impurity concentrations are applied to different locations within the well region. The first well region has a first impurity concentration optimized for low ON resistance, while the second well region has a second impurity concentration optimized for short-circuit current suppression. This local differentiation of properties resolves the contradiction by allowing each region to optimize for its specific function.
2Loss of energy
If the impurity concentration of the well region is reduced to reduce Joule heat, then the short circuit tolerance is improved, but the ON resistance increases
Solution Approach 1:
The well region is segmented into first and second well regions with different impurity concentrations. The first well region maintains high carrier concentration to ensure low ON resistance, while the second well region has reduced impurity concentration to suppress short-circuit current and reduce Joule heat generation during fault conditions.
Solution Approach 2:
Different impurity concentrations are locally applied within the well region to achieve different functional outcomes. The first well region is optimized for electrical conductivity (low ON resistance), while the second well region is optimized for thermal management (Joule heat suppression) during short-circuit events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device effectively reduces short-circuit current and Joule heat while maintaining low ON resistance by dynamically adjusting the current path through p-n junctions and Schottky junctions, enhancing short circuit tolerance without increasing ON resistance.
Implementation Method 1
a multilayer region formed in a region between the trench gate structure and the source region in the semiconductor layer, the multilayer region including a second conductivity type impurity region formed in the surface layer portion of the first principal surface of the semiconductor layer and a first conductivity type impurity region formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region
Implementation Method 2
a source electrode formed at the first principal surface of the semiconductor layer and electrically connected to the source region and the first conductivity type impurity region, the source electrode forming a Schottky junction with the first conductivity type impurity region
Implementation Method 3
When a short-circuit voltage is applied between the semiconductor layer and the source region, a depletion layer extends from the p-n junction portion formed between the second conductivity type impurity region and the first conductivity type impurity region into the first conductivity type impurity region
Implementation Method 4
the semiconductor device can be destroyed by Joule heat due to the short-circuit voltage and the short-circuit current in a time as short as, for example, several μsec to several tens μsec
Data Source
AI summary
A semiconductor device 1 includes a trench gate structure 6 formed in a surface layer portion of a first principal surface of a semiconductor layer. A source region 10 and a well region 11 are formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure 6. The well region 11 is formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region 10. A channel is formed along the trench gate structure 6 in a portion of the well region 11. A multilayer region 22 is formed in a region between the trench gate structure 6 and the source region 10 in the semiconductor layer. The multilayer region 22 has a p type impurity region 20 formed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity region 21 formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region 20.