Trench Gate Semiconductor Device Self-Aligned Contact Formation
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices with trench gate structures is the variability in on-resistance due to inaccuracies in mask alignment during the formation of contact trenches, which affects the gate threshold voltage and channel density, leading to increased resistance.
Innovation Solution
A method involving the formation of sidewalls adjacent to interlayer insulating films without the need for mask alignment, allowing for self-aligned etching of contact trenches and reducing dimensional variations, thereby minimizing the impact on on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mask alignment is used for forming contact trench, then manufacturing process can be completed, but dimensional variation increases causing on-resistance to increase
Solution Approach 1:
The method forms a preliminary structure (trench contact structure with p+-type contact layer) before final device operation, establishing precise geometric relationships through self-alignment. The contact trench is formed to extend through the n+-type source layer to the p-type base layer, with the p+-type contact layer positioned at the bottom, creating a predetermined spatial arrangement that eliminates subsequent alignment variability.
Solution Approach 2:
The invention employs self-aligned fabrication where the contact trench positioning is determined by the trench gate structure itself rather than external mask alignment. The process uses the existing trench gate and interlayer insulating film as reference structures, allowing the contact trench to automatically align with correct positioning without requiring separate mask layers, thereby eliminating mask alignment errors.
2Reliability
If p+-type contact layer is provided in contact trench bottom, then hole ejection resistance is reduced, but mask alignment variation causes gate threshold voltage to increase
Solution Approach 1:
The p+-type contact layer is formed through self-aligned ion implantation where the trench gate structure serves as the alignment reference. The implantation process uses the trench gate and interlayer insulating film as built-in masks, ensuring that the contact layer is automatically positioned at the correct distance from the gate without requiring external mask alignment, thus maintaining precise spatial control while achieving low hole ejection resistance.
3Quantity of substance
If trench gate structure is used, then channel density is increased, but manufacturing complexity increases due to additional alignment requirements
Solution Approach 1:
The invention merges multiple functions into unified structures: the trench gate structure simultaneously serves as the gate electrode, the alignment reference for contact trench formation, and the mask for p+-type contact layer implantation. The interlayer insulating film combines electrical isolation with mechanical support functions. This consolidation eliminates separate alignment steps while maintaining high channel density achieved by the trench gate configuration.
Solution Approach 2:
The trench gate structure is designed to perform multiple functions: it provides the gate electrode function for device operation, serves as the alignment reference structure for subsequent contact trench formation, and acts as the mask structure for p+-type contact layer ion implantation. This multi-functionality reduces the number of separate components and alignment steps required, simplifying the overall manufacturing process while maintaining high channel density.
Data Source
AI summary
According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer.