Trench Gate Semiconductor Device Reducing Switching Loss

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor devices with trench gate structures face challenges in reducing ON-state voltage drop and switching loss due to high capacitance between the gate and emitter, which increases power generation loss and requires complex fabrication processes, leading to reliability and yield issues.

Innovation Solution

A semiconductor device with gate electrodes along both side walls of trenches, where the polysilicon film is etched back without using a resist mask, reducing the number of process steps and preventing resist residue, and a shield electrode is connected to the emitter electrode to decrease capacitance, thereby improving turn ON characteristics and reducing switching loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a complex fabrication process with resist masks is used to form gate electrodes, then manufacturing precision can be improved, but the number of process steps increases and reliability decreases due to resist residue

Engineering Contradiction:
Improvegate electrode positioningVSAvoidfabrication process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The resist mask step is extracted and eliminated from the fabrication process. Gate electrode positioning is achieved through direct self-alignment during the trench formation and electrode deposition processes, removing the intermediate masking step that causes complexity and reliability issues while maintaining positioning precision.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The fabrication process is designed to be self-aligning, where the gate electrode positions are automatically determined by the trench geometry and deposition conditions rather than requiring external masking. This self-service approach simplifies the process while ensuring consistent electrode placement.

Inventive Principle:
Principle #25Self-service

2Loss of energy

If the capacitance between gate and emitter is large, then the channel density and conductivity modulation are improved, but the charging/discharging time increases and power generation loss increases

Engineering Contradiction:
ImproveON-state voltage dropVSAvoidcharging/discharging time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

Different regions of the gate structure have optimized local properties: front surface gate electrodes provide broad-area control for conductivity modulation, while side wall gate electrodes provide localized channel enhancement. This local quality differentiation allows effective channel control with reduced overall capacitive loading compared to uniform high-density side wall gating.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution shortens the fabrication process, enhances reliability, and decreases switching loss by directly connecting gate and shield electrodes to metal electrodes, eliminating the need for resist masks and reducing resist residue, while improving turn ON characteristics and reducing capacitance between the gate and emitter.

Implementation Method 1

electric charges are stored in the gate electrode 109

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

when the electric charges stored in the gate electrode 109 are discharged to the gate drive circuit, the portion that inverted to the n-type, out of the p-base region 105, returns to the p-type

Methodology Applied
Scientific EffectCapacitance discharge: Capacitance

Data Source

PatentEP2985790B1Semiconductor device and semiconductor device manufacturing method
Publication Date: 2021.06.09 FUJI ELECTRIC CO LTD
  • EP2985790B1 patent drawingFigure 1A
  • EP2985790B1 patent drawingFigure 1B
  • EP2985790B1 patent drawingFigure 2

AI summary

A p-layer disposed on a surface layer of one of n- drift layers is separated into a p-base-region (5) and a floating p-region (6) by a plurality of trenches (4). A first gate electrode (9a) is disposed on a side wall of the trench (4) on the p-base-region (5) side via a first insulation film (8a), and a shield electrode (9b) is disposed on a side wall of the trench (4) on the floating p-region (6) side via a second insulation film (8b). Between the first gate electrode (9a) which is conductively connected to a gate runner (13) via a contact plug embedded in a first contact hole (10a) and the shield electrode (9b) which is conductively connected to an emitter electrode (11) via a contact plug embedded in a second contact hole (10b), an insulation film (20) which reaches from the front surface of the substrate to the bottom surface of the trench (4) is disposed. Hence, the fabrication process can be shortened, and a highly reliable semiconductor device with low switching loss can be provided.