Trench Gate Semiconductor Device Uniform Channel Length
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Solution Overview
Problem
The channel length variation in semiconductor devices with trench gates due to non-uniform etch depth and ion implantation in semiconductor wafers leads to process uniformity issues and gate length variations.
Innovation Solution
A semiconductor device structure with a trench gate and a fabrication method involving angled implantations of doping impurities through the side walls, with a gate dielectric layer and an insulating cover layer to control doping concentrations and dimensions, ensuring uniform channel lengths and reduced capacitance between the gate and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If one-step etching is used to form the trench, then the fabrication process is simple, but the trench depth varies significantly between center and edge sections, causing channel length variation
Solution Approach 1:
The single etching step is divided into multiple etching steps with different conditions. The first etching step forms an initial trench structure, and the second etching step adjusts the depth to achieve uniform channel lengths across the wafer, thereby resolving the contradiction between process simplicity and depth uniformity.
Solution Approach 2:
The etching parameters (such as etchant concentration, temperature, or power) are changed between steps to control the etching rate and achieve the desired trench depth profile. This allows the process to maintain simplicity while achieving precise depth uniformity across different wafer sections.
2Reliability
If ion implantation is performed to create doped areas, then the channel length is defined, but the channel length varies due to non-uniform implantation depth
Solution Approach 1:
The ion implantation process is segmented into multiple implantation steps with different angles and energies. The first implantation defines the basic channel structure, while subsequent implantations adjust the doping profile to ensure uniform channel lengths across the wafer, resolving the uniformity issue.
Solution Approach 2:
Angled ion implantation is used instead of vertical implantation. By implanting at specific angles through the trench sidewalls, the doping profile is asymmetrically controlled to achieve uniform channel lengths despite variations in trench depth across the wafer.
3Device complexity
If the trench is fully filled with gate electrode material, then the gate structure is complete, but the capacitance between gate and drain increases
Solution Approach 1:
Instead of fully filling the trench with gate electrode material, the excess material is removed to create a partially filled trench structure. This extraction of unnecessary material reduces the gate-drain overlap and consequently decreases the parasitic capacitance while maintaining the essential gate function.
Solution Approach 2:
The trench is partially filled with gate electrode material rather than being completely filled. This partial action is sufficient to form the gate structure needed for device operation while avoiding the excessive material that would increase capacitance and create harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves uniform channel lengths, reduces gate-induced drain leakage, and decreases junction resistance while maintaining high device density and controlling word line coupling and cross-talk links.
Implementation Method 1
a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer
Implementation Method 2
a first angled implantation is then carried out to doping impurities into the substrate through the side walls in the partially filled trench
Data Source
AI summary
A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.