Trench Gate Semiconductor Device Withstand Voltage
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Solution Overview
Problem
Existing trench-gate semiconductor devices face challenges in dispersing electric fields, leading to electric field concentration and potential dielectric breakdown, particularly at the upper and lower edges of the gate trench, which affects the reliability and withstand voltage of the gate insulating film.
Innovation Solution
The semiconductor device incorporates an inclined or circular surface at the upper edge of the gate trench and a thicker bottom-surface insulating film, along with a planar insulating film, to disperse electric fields and reduce capacitance, while also using a second conductive-type layer in the inactive region to form a depletion layer and alleviate electric field concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional trench-gate structure with vertical walls is used, then the manufacturing process is simple, but electric field concentration occurs at the upper and lower edges of the gate trench leading to dielectric breakdown
Solution Approach 1:
The patent applies curvature by forming an inclined surface at the upper edge of the gate trench instead of a sharp corner. This curved transition disperses the electric field concentration that would otherwise occur at the upper edge corner, preventing dielectric breakdown and improving the withstand voltage of the gate insulating film while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies local quality by making the bottom-surface insulating film thicker than other portions of the side-surface insulating film. This localized thickening specifically addresses the high electric field stress at the bottom of the gate trench where dielectric breakdown is most likely to occur, while keeping other areas optimized for different functions
2Speed
If the gate insulating film is made thinner to reduce gate capacitance, then switching speed improves, but dielectric breakdown risk increases at the trench edges
Solution Approach 1:
The patent implements local quality by varying the thickness of the bottom-surface insulating film to be greater than other portions. This allows the overall gate insulating film to be thin enough for fast switching while the locally thickened bottom portion provides enhanced dielectric strength at the critical high-field region, preventing breakdown
Solution Approach 2:
The inclined surface at the upper edge creates a curved transition that disperses electric field concentration. This allows the gate insulating film to be made thinner overall for faster switching without concentrating enough field at sharp corners to cause dielectric breakdown
3Area of stationary object
If gate wirings are positioned close to the gate trench for compact design, then device area is reduced, but electric field concentration increases causing breakdown
Solution Approach 1:
The inclined surface at the upper edge of the gate trench creates a curved geometry that disperses electric field lines. This allows gate wirings to be positioned closer to the trench for compact design without the field concentration at sharp corners that would otherwise cause dielectric breakdown
Solution Approach 2:
The localized thickening of the bottom-surface insulating film provides enhanced dielectric protection at the critical bottom region where gate wirings are typically positioned, enabling closer wiring placement while maintaining breakdown voltage through locally enhanced insulation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively disperses electric fields, reduces the risk of dielectric breakdown, and enhances the withstand voltage and reliability of the gate insulating film, improving the overall performance of the semiconductor device.
Implementation Method 1
it is possible to disperse the electric field applied to the upper edge when the gate is turned on to within the inclined surface to alleviate an electric field concentration
Implementation Method 2
it is possible to reduce the capacitance of a capacitor arranged by the gate electrode and the semiconductor layer facing each other via the bottom-surface insulating film. As a result, it is possible to reduce the capacity of the entire gate (gate capacitance)
Implementation Method 3
using a second conductive-type layer in the inactive region to form a depletion layer and alleviate electric field concentrations
Data Source
Figure 1(a)~1(b)
Figure 2(a)~2(c)
Figure 3~4
AI summary
The technical problem to be solved is to provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for manufacturing the semiconductor device. The solution corresponds to a semiconductor device (1) including: an n-type substrate (2) having a gate trench (9) formed therein; a gate insulating film (16), which integrally includes a side-surface insulating film (18) and a bottom-surface insulating film (19); and a gate electrode (15) which is embedded in the gate trench (9), and which selectively has an overlap portion (17) that overlaps, at the upper edge (26), the surface (21) of the substrate (2). In the side-surface insulating film (18), an overhung portion (27) that is selectively thick compared with other portions of the side-surface insulating film (18) is formed such that the overhung portion protrudes, at the upper end edge (26), toward the inside of the gate trench (9).