Trench-Gate Semiconductor Layout for Low On-Resistance and Short-Circuiting

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Solution Overview

Problem

Existing semiconductor components, such as silicon carbide (SiC) trench-gate-power MISFETs, face challenges in achieving good forward properties with low area-specific resistance while maintaining resistance to short-circuiting and limiting maximum field strength in the insulator to acceptable values.

Innovation Solution

The semiconductor component incorporates a p-doped second shielding region arranged vertically below the gate trench, which is designed to extend horizontally to the p-doped first shielding region in delimited regions, forming additional channel regions to compensate for the lack of channel formation in the contact region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a gate trench is introduced to improve switching characteristics and control, then the switching performance is improved, but the manufacturing complexity and difficulty of achieving low area-specific resistance increase

Engineering Contradiction:
Improveswitching performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is segmented into multiple functional regions including gate trenches, first shielding regions, and second shielding regions. Each segment performs a specific function: gate trenches provide voltage control, first shielding regions limit maximum field strength, and second shielding regions enhance short-circuit resistance. This segmentation allows independent optimization of each region to resolve the contradiction between switching performance and manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doping types and concentrations are applied to different regions: p-doping in shielding regions for field control, n-doping in channel regions for conduction. The gate trench geometry and insulation thickness are locally optimized based on specific functional requirements. This local quality approach enables simultaneous achievement of low area-specific resistance and acceptable manufacturing complexity by tailoring properties to local needs.

Inventive Principle:
Principle #3Local quality

2Reliability

If shielding regions are added to limit maximum field strength and improve short-circuit resistance, then reliability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveresistance to short-circuitingVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first shielding regions and second shielding regions are merged with the gate trench structure to form an integrated shielding system. The p-doped regions are combined with the gate trench geometry, and the insulation layer is integrated into the same structural framework. This merging reduces the number of separate components and simplifies manufacturing while maintaining the dual function of field strength limitation and short-circuit resistance enhancement.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shielding regions serve multiple functions simultaneously: they limit maximum field strength in the insulation, enhance resistance to short-circuiting, and provide structural support for the gate electrode. The p-doped regions act as both electrical shields and mechanical anchors. This multi-functionality reduces device complexity by eliminating the need for separate components for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the gate trench geometry is optimized to form additional channel regions, then switch-on resistance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveswitch-on resistanceVSAvoidtrench geometry precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate trench geometry is pre-designed with specific dimensions and configurations that automatically form the desired channel regions during the doping and insulation processes. The trench width, depth, and curvature are predetermined to ensure proper channel formation without requiring additional precision steps. This preliminary action approach reduces manufacturing precision requirements while achieving low switch-on resistance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate trench parameters such as width, depth, and curvature radius are optimized to create favorable conditions for channel formation. By adjusting these geometric parameters, the device achieves low switch-on resistance through enhanced channel regions without imposing excessive precision requirements. The parameter optimization allows for tolerance in manufacturing while maintaining performance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the resistance to short-circuiting and maintains low switch-on resistance by forming additional channel regions, thereby improving the overall performance and reliability of the semiconductor component.

Implementation Method 1

forming additional channel regions to compensate for the lack of channel formation in the contact region

Methodology Applied
Scientific EffectCharge carrier conduction: Conduction (electrical)

Data Source

PatentUS20250031409A1Semiconductor component and method for producing a semiconductor component
Publication Date: 2025.01.23 ROBERT BOSCH GMBH
  • US20250031409A1 patent drawing
  • US20250031409A1 patent drawing
  • US20250031409A1 patent drawing

AI summary

A semiconductor component, in particular a transistor. The semiconductor component includes: source and drain layers doped according to a first type, a channel layer located vertically between the source layer doped and the drain layer, and a gate trench, which extends vertically from the source layer to the drain layer and adjoins the channel layer and at least a portion of the source layer. A first shielding region doped according to a second type, extends vertically from the source layer, or a semiconductor surface adjoining it, to the drain layer, and a second shielding region doped according to the second type, is arranged vertically below a bottom of the gate trench, wherein the gate trench and the second shielding region are designed such that, in one or more delimited regions, the second shielding region extends horizontally at least to the first shielding region.