Trench Gate Termination in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices with trench gate structures face challenges in maintaining charge balance and breakdown voltage due to the termination of the gate trench, which can lead to reduced reliability and efficiency.
Innovation Solution
The semiconductor device incorporates a second parallel pn layer with a shifted repetition cycle, where the trench gate termination is covered by a p-type region of the second parallel pn layer, maintaining charge balance and mitigating the electric field at the trench termination, thereby enhancing breakdown voltage and gate reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate trench is terminated in the intermediate region between active region and edge termination region, then the manufacturing process is simplified, but the charge balance is disrupted and breakdown voltage is reduced
Solution Approach 1:
The patent introduces a second parallel pn layer stacked in the vertical dimension above the first parallel pn layer. The gate trench terminates in the second layer rather than the first, transferring the termination point to a different spatial dimension (vertical stacking) while maintaining electrical functionality through the stacked configuration of alternating n-type and p-type regions.
Solution Approach 2:
The second parallel pn layer acts as an intermediary structure that mediates between the gate trench termination and the edge termination region. By terminating the gate trench in this intermediate second layer, the patent avoids direct termination in the first layer's intermediate region, thus preventing charge balance disruption while still simplifying manufacturing compared to extending the trench to the edge termination region.
2Reliability
If the gate trench extends to the edge termination region, then the breakdown voltage is maintained, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the parallel pn layer structure into multiple stacked layers (first parallel pn layer and second parallel pn layer). This segmentation allows the gate trench to terminate in the upper second layer rather than extending through the entire structure to the edge termination region, reducing device complexity while maintaining breakdown voltage through the segmented stacked configuration.
Solution Approach 2:
By stacking parallel pn layers in the vertical dimension, the patent creates a three-dimensional structure where the gate trench can terminate at different vertical levels. Terminating in the second layer instead of extending to the edge termination region reduces complexity while the vertical stacking maintains the electrical field distribution needed for breakdown voltage.
3Ease of manufacture
If the gate trench terminates in the first parallel pn layer, then the manufacturing process is simpler, but charge balance is disrupted leading to reduced breakdown voltage
Solution Approach 1:
The patent resolves the charge balance issue by moving the gate trench termination to a different vertical dimension - specifically, terminating in the second parallel pn layer stacked above the first layer. This vertical displacement allows the trench to avoid disrupting the charge balance in the first layer while maintaining manufacturing simplicity.
Solution Approach 2:
The second parallel pn layer serves as an intermediary that absorbs the gate trench termination without disrupting the charge balance of the first parallel pn layer. The stacked configuration allows the second layer to handle the termination effects while the first layer maintains its charge balance integrity.
Data Source
AI summary
An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.