Trench-Gate Vertical Thin-Body Transistor for Low Ioff Scaling
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Solution Overview
Problem
Conventional transistor structures face challenges in reducing standby current (Ioff) below 1 pA, especially as device dimensions shrink, due to increased leakage current paths, difficulty in aligning LDD junction edges, non-uniform dopant distribution, and vulnerability of fin structures during processing, which hinder the transition to Tera-Scale Integration (TSI).
Innovation Solution
A 3D transistor structure with multiple vertical thin semiconductor bodies and a trench-based design, featuring a gate conductive layer and dielectric layer, where the gate dielectric layer covers the trench bottom and sidewalls, and the gate conductive layer is filled within the trench, creating conductive channels and suppressing leakage currents, while maintaining effective channel length and reducing gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FinFET or Tri-gate structures are used to increase integration density, then transistor integration capacity is improved, but standby current (Ioff) increases to unacceptable levels (5-10 pA instead of <1 pA)
Solution Approach 1:
The patent transitions from conventional planar or simple 3D FinFET structures to a multi-layer stacked transistor architecture where multiple transistor layers are vertically stacked. This dimensional change allows achieving Tera-Scale Integration (trillions of transistors) while maintaining low standby current by providing superior gate control over the channel in each stacked layer, thereby resolving the contradiction between high integration density and low leakage current.
2Productivity
If device gate length is scaled down to increase integration, then transistor density is improved, but OFF state current (Ioff) becomes harder to reduce due to increased leakage paths
Solution Approach 1:
The patent employs vertical stacking of multiple transistor layers to achieve high density without further reducing gate length. Each stacked layer maintains adequate gate length for reliable OFF state control while the vertical arrangement provides enhanced gate-to-channel control, thus achieving high transistor density without sacrificing OFF state current control.
Solution Approach 2:
The patent implements nested structures where multiple transistor layers are stacked within a compact vertical space. Each transistor layer is nested within the overall stacked architecture, allowing high integration density while maintaining proper gate control for low leakage current in each nested layer.
3Ease of manufacture
If ion-implantation plus thermal annealing is used to form LDD regions, then doping is achieved, but LDD regions penetrate underneath gate structure causing effective channel length shortening
Solution Approach 1:
The patent forms the gate structure first, then uses the gate as a mask for subsequent ion implantation of LDD regions. This preliminary gate formation ensures that LDD regions are deposited only in designated areas and do not penetrate underneath the gate structure, thereby maintaining precise effective channel length control while still achieving proper doping.
Solution Approach 2:
The gate structure serves as an intermediary mask during the ion implantation process. It mediates between the ion source and the substrate, allowing LDD regions to be formed in controlled positions without penetrating the gate, thus resolving the conflict between doping capability and channel length precision.
4Reliability
If fin structure height is increased to improve device performance, then transistor performance is enhanced, but fin structure becomes vulnerable and collapses during subsequent processing
Solution Approach 1:
The patent distributes transistor channels across multiple vertical layers stacked horizontally rather than relying on a single tall fin structure. This dimensional redistribution maintains device performance through multiple channels while each layer has moderate height, preventing structural vulnerability and collapse during processing.
Solution Approach 2:
The patent segments a single tall fin structure into multiple shorter stacked layers. Each segment (layer) has reduced height and thus improved structural stability, while the collective arrangement of segments maintains or enhances overall transistor performance through multiple parallel channels.
Data Source
Figure 1
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Figure 3(a)~3(c)
AI summary
A transistor structure includes a body and a gate structure. The body has a single convex structure, wherein the convex structure is made of a first semiconductor material, and a trench is formed in the single convex structure. The gate structure has a gate conductive layer and a gate dielectric layer, wherein the gate conductive layer is across over the single convex structure, and a portion of the gate conductive layer is filled in the trench.