Trench Gate Transistor Fabrication for High-Voltage Reliability
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Solution Overview
Problem
High-voltage MOS transistors face challenges in scaling down while maintaining high breakdown voltage, which complicates integration density in semiconductor devices.
Innovation Solution
A method of fabricating semiconductor devices involves forming gate trenches, implanting ions to create gate electrodes and impurity regions, and using spacer insulating layers to reduce damage, allowing for the formation of high-concentration source/drain regions and gate electrodes, enabling the creation of high-voltage transistors with improved breakdown voltage and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage MOS transistors are designed to have high breakdown voltage, then breakdown voltage is improved, but device area increases and integration density deteriorates
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional trench gate transistors by etching vertical trenches into the semiconductor substrate. This vertical dimension allows the gate to wrap around the channel region, increasing the effective gate area and control without expanding the planar footprint, thus improving breakdown voltage while maintaining compact device area
Solution Approach 2:
The trench gate structure nests the gate electrode within a vertically etched trench that extends into the substrate. The gate wraps around and encloses the channel region from multiple sides, creating a nested configuration where the gate is positioned both above and around the active channel area, maximizing voltage control within minimal planar space
2Reliability
If ions are implanted to form gate electrodes and impurity regions, then transistor performance is improved, but damage to the semiconductor substrate increases
Solution Approach 1:
A buffer region is formed in the semiconductor substrate before ion implantation, positioned between the active region and the trench gate. This buffer region acts as a cushion that absorbs and mitigates the damage caused by ion implantation, protecting the active region from excessive damage while still allowing the formation of high-concentration source/drain regions and gate electrodes
Solution Approach 2:
The buffer region serves as an intermediary layer between the ion implantation process and the active semiconductor region. It mediates the harmful effects of ion implantation by providing a sacrificial zone that can be damaged without compromising the integrity and functionality of the active transistor region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the area occupied by high-voltage transistors, enhances integration density, and allows for the simultaneous formation of high-concentration source/drain regions and gate electrodes, thereby improving breakdown voltage and reducing leakage current.
Implementation Method 1
first implanting ions in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode
Data Source
AI summary
Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode.