Trench Gate Transistor Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
Trench gate transistors in DRAM devices face short-channel effects and increased parasitic capacitance due to the wide opposing area between the gate electrode and substrate, leading to deteriorated rise characteristics and increased chip size.
Innovation Solution
A semiconductor device with a trench gate transistor featuring a first gate electrode in the lower part of a groove with a gate insulation film, side walls on the inner groove walls above the first gate electrode, and a second gate electrode in contact with the side walls and top surface of the first gate electrode, using a composite film of gate oxide and groove side walls to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench gate transistor with a wide gate electrode opposing area is used to suppress short-channel effects, then the channel length is increased and short-channel effects are suppressed, but the parasitic capacitance of the word line increases leading to deteriorated rise characteristics
Solution Approach 1:
The gate electrode is divided into two separate gate electrodes positioned at different depths within the trench. The first gate electrode is located at the bottom of the trench and the second gate electrode is positioned higher up, allowing each gate to control different portions of the channel independently. This segmentation reduces the parasitic capacitance while maintaining effective channel control for suppressing short-channel effects.
Solution Approach 2:
The patent transitions from a conventional planar gate structure to a three-dimensional trench gate structure with gates positioned at different vertical levels within the trench. This dimensional change allows the gate electrodes to be distributed along the depth of the trench, reducing the opposing area between the gate and substrate while maintaining channel control effectiveness.
2Reliability
If the trench gate structure is implemented to increase channel length, then short-channel effects are reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The trench gate is segmented into two gate electrodes at different positions within the trench, allowing independent optimization of each gate's function. This segmentation simplifies the manufacturing process by enabling separate formation and adjustment of each gate, reducing the overall device complexity while maintaining the benefits of the trench structure.
Solution Approach 2:
Different regions of the trench are assigned different functions: the bottom region contains the first gate electrode for primary channel control, while the upper region contains the second gate electrode for additional control and capacitance reduction. This local differentiation optimizes performance while simplifying the overall structure compared to a uniform complex design.
3Object-generated harmful factors
If the gate electrode opposing area is reduced to decrease parasitic capacitance, then rise characteristics are improved, but the ability to suppress short-channel effects is weakened
Solution Approach 1:
By positioning gate electrodes at different vertical levels within the trench rather than having a single wide gate, the patent reduces the gate-substrate opposing area and thus parasitic capacitance. Simultaneously, the distributed gates maintain effective channel control along the trench depth, preserving short-channel effects suppression capability.
Solution Approach 2:
The gate function is segmented into multiple electrodes at different positions, reducing the total opposing area between gate and substrate while maintaining channel control. The first gate at the bottom and the second gate higher up work together to suppress short-channel effects without the excessive parasitic capacitance of a single wide gate.
Data Source
AI summary
The present invention provides a trench gate Tr having a first gate electrode and a second gate electrode in the inside of a groove. The first gate electrode is provided in a groove lower part defining a channel of the Tr with a gate oxide film interposed between the first gate electrode and the substrate. The second gate electrode is provided in a groove upper part facing a Tr impurity diffusion layer, with a gate oxide film and a groove side wall film interposed between the second gate electrode and the groove upper part. The provision of the composite film consisting of the gate oxide film and the groove side wall between gate electrode and the substrate in the groove upper part enables reduction of the parasitic capacitance of the gate electrode.