Trench-Gate Transistor with Thick Bottom Insulator
Solution Overview
Problem
Conventional trench-gate transistors face challenges in increasing drive current, reducing parasitic capacitance, and improving circuit delay due to the short channel effect and high substrate concentration, which deteriorates refresh characteristics in DRAM.
Innovation Solution
A semiconductor device with a trench-gate transistor design featuring a Shallow Trench Isolation (STI) region, a gate trench, a thick insulating film on the bottom of the trench, and a thin gate insulating film on the side surfaces, allowing the semiconductor substrate to function as a channel region, thereby reducing parasitic capacitance and enhancing drive current without increasing element area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length is reduced to decrease cell size, then the cell area is reduced, but the short channel effect increases and sub-threshold current increases
Solution Approach 1:
The invention transitions from a planar gate structure to a three-dimensional trench gate structure by etching a groove into the semiconductor substrate. This vertical dimension allows the gate to extend deeper into the substrate, providing better electrostatic control over the channel and suppressing the short channel effect even when the gate length is reduced for smaller cell sizes.
Solution Approach 2:
The gate electrode is nested within the trench groove formed in the semiconductor substrate. This nesting structure allows the gate to be embedded in the substrate, increasing the effective gate-channel interaction area and improving control over the channel region, thereby reducing sub-threshold current while maintaining compact cell dimensions.
2Reliability
If substrate concentration is increased to suppress sub-threshold current, then sub-threshold current is reduced, but junction leakage increases
Solution Approach 1:
The invention applies different impurity concentrations to different regions: the channel region maintains low substrate concentration to minimize junction leakage, while the drain region has higher impurity concentration to ensure proper junction characteristics. This localized differentiation allows suppression of sub-threshold current through the trench gate structure rather than through uniform substrate doping.
3Reliability
If conventional trench-gate transistor is used to secure effective channel length, then short channel effect is suppressed, but drive current is insufficient and parasitic capacitance is high
Solution Approach 1:
The invention optimizes multiple parameters simultaneously: the trench depth is set to 0.5-2.0 times the gate length to achieve optimal electrostatic control, the gate electrode width is optimized to balance drive current and capacitance, and the insulating film thickness is carefully controlled. These parameter optimizations enable both suppression of short channel effect and improvement of drive current characteristics.
Data Source
AI summary
A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region.