Trench-Gated Vertical Power Semiconductor for Higher Cell Density
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Solution Overview
Problem
Existing vertical semiconductor power devices face challenges in miniaturization due to the large area occupied between trenches and source contacts, limiting device density and efficiency.
Innovation Solution
A vertical semiconductor power device design where a gate electrode is surrounded and covered by a dielectric layer within a trench, reducing direct contact with the shield electrode and substrate, and a manufacturing method involving trench formation, dielectric layer deposition, and gate electrode placement to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional trench structure is used with direct contact between gate electrode, shield electrode, and substrate, then the device structure is simple and manufacturing is easier, but the area between trenches and source contacts becomes large, limiting device miniaturization
Solution Approach 1:
The gate electrode is nested within the dielectric layer that fills the trench, creating a nested configuration where the dielectric layer surrounds the gate electrode. This nesting approach reduces the horizontal space required while maintaining electrical isolation, thereby reducing the area between trenches and source contacts without significantly increasing structural complexity.
Solution Approach 2:
The invention transitions from a conventional planar arrangement to a three-dimensional configuration by embedding the gate electrode within the dielectric-filled trench. This vertical integration into the trench depth dimension reduces the horizontal footprint and minimizes the area between trenches and source contacts.
2Reliability
If the gate electrode directly adjoins the shield electrode and substrate, then the manufacturing process is simpler, but the device resistance increases and performance decreases
Solution Approach 1:
The dielectric layer acts as an intermediary material between the gate electrode and the shield electrode/substrate. This intermediate layer provides electrical isolation, preventing direct contact that would increase resistance, while still allowing the gate electrode to be formed within the trench structure through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the distance between trenches, decreases the total surface area, and lowers device resistance, enhancing miniaturization and performance.
Implementation Method 1
a first gate electrode, arranged in the first in-trench dielectric layer and around the first shield electrode, wherein the first gate electrode is wrapped by the first in-trench dielectric layer, such that the first gate electrode does not directly adjoin the first shield electrode and the substrate
Data Source
AI summary
A vertical semiconductor power device is provided, which includes a substrate having a first surface and a second surface opposite to each other. A trench extends from the second surface toward the first surface. An in-trench dielectric layer is disposed along an inner surface of the trench. A shield electrode is disposed in the trench and is surrounded by the in-trench dielectric layer. A gate electrode is disposed in the in-trench dielectric layer and surrounds the shield electrode. The gate electrode is surrounded by the in-trench dielectric layer without adjoining the shield electrode and the substrate. A method for making the vertical semiconductor power device is also provided.