Trench IGBT Emitter Layout for Lower Pinch Resistance
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Solution Overview
Problem
Existing semiconductor devices with trench gate type IGBTs face issues of increased pinch resistance and decreased latch-up tolerance due to the emitter layer's H-shaped configuration, which is not suitable for reducing latch-up.
Innovation Solution
The semiconductor device incorporates a design where the emitter layer is discretely arranged in a mesa region between adjacent active trenches, with a contact layer disposed between regions of the emitter layer, allowing current to flow in multiple directions and reducing latch-up tolerance, while maintaining high saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the emitter layer is disposed in an H shape by partially narrowing the width, then the saturation current increases, but the pinch resistance increases and latch-up tolerance decreases
Solution Approach 1:
The emitter layer is segmented into multiple discrete regions arranged in an H-shape pattern, with narrow portions connecting wider regions. This segmentation allows the current to flow through multiple paths while maintaining low pinch resistance at the narrow portions, thereby reducing latch-up risk without sacrificing saturation current.
Solution Approach 2:
Different regions of the emitter layer have different widths to serve different functions: wider regions provide low resistance for current flow, while narrower connecting portions provide sufficient spacing to prevent latch-up. This local variation in geometry optimizes both saturation current and latch-up tolerance simultaneously.
2Reliability
If the emitter layer is disposed in an H shape, then the saturation current increases, but the latch-up tolerance decreases
Solution Approach 1:
The emitter layer is divided into discrete regions connected by narrow portions, creating multiple current paths. This segmentation increases saturation current by providing parallel conduction paths while the narrow connections maintain sufficient spacing to prevent latch-up, thus improving reliability without sacrificing productivity.
Solution Approach 2:
The emitter layer transitions from a simple linear configuration to a two-dimensional H-shaped pattern, utilizing both width and length dimensions. This dimensional expansion creates multiple current paths that increase saturation current while the narrow connecting portions in the width direction maintain latch-up tolerance.
Data Source
AI summary
In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.