Trench IGBT Emitter Stripe Width Optimization for RBSOA Stability
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Solution Overview
Problem
Trench IGBTs face challenges in maintaining a stable reverse bias safe operation area (RBSOA) and suppressing variations in saturation current due to issues with emitter region width and resistance, leading to potential element breakdown and latch-up phenomena.
Innovation Solution
A semiconductor device with a trench gate structure featuring a combination of effective and dummy trench regions, where the emitter layer is formed in stripes orthogonal to the trenches, with a specific width and resistance condition satisfied to ensure stable operation and secure RBSOA, by setting the width of the emitter layer to be less than or equal to a calculated maximum value based on sheet resistance and trench pitch, and using an exponential function to account for decimation ratio effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the emitter region is formed in stripes orthogonal to the trench region to reduce saturation current, then the saturation current is reduced, but the reverse bias safe operation area (RBSOA) becomes insufficient and element breakdown may occur
Solution Approach 1:
The emitter region is designed with different widths in different regions: a first width in the contact region with the channel P region and a second width (narrower) in the side wall region of the trench. This local differentiation allows the contact region to provide sufficient area for low saturation current while the side wall region maintains appropriate geometry for stable RBSOA operation, preventing element breakdown during reverse bias conditions
2Quantity of substance
If the width of the emitter region is reduced to reduce saturation current, then the saturation current decreases, but the on-voltage increases and the device cannot operate at low voltage
Solution Approach 1:
By making the emitter region width different in the contact region versus the side wall region, the design allows the contact region to have sufficient width for low on-voltage operation while the overall emitter area is controlled to maintain low saturation current. The side wall region's narrower width contributes to area control without excessively increasing on-voltage, as the contact region provides the primary conduction path
3Power
If the area ratio between the emitter region and the channel P region is adjusted to reduce on-voltage, then the on-voltage decreases, but the saturation current cannot be controlled
Solution Approach 1:
The emitter region width is differentiated between the contact region (first width) and side wall region (second width). The contact region's width is optimized to maintain an appropriate area ratio with the channel P region for low on-voltage operation, while the side wall region's narrower width helps control the total emitter area to limit saturation current. This local differentiation decouples the two parameters that were previously coupled in uniform emitter designs
4Quantity of substance
If the emitter region is formed along the trench side wall to increase saturation current, then the saturation current increases, but variations in saturation current occur due to mask misalignment
Solution Approach 1:
The emitter region is designed with a narrower width in the side wall region compared to the contact region. This differentiation reduces the sensitivity to mask misalignment in the side wall region, as the narrower width contributes less to total area variations. The contact region maintains sufficient width for performance while the overall design tolerates alignment variations better, reducing saturation current variations across different device locations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses variations in saturation current, ensures a secure RBSOA, and prevents latch-up, allowing for stable and low on-voltage operation of the semiconductor device.
Implementation Method 1
A channel is formed in the base layer by applying a voltage to the gate electrode
Implementation Method 2
Minority carriers (holes) are injected from the collector layer to the drift layer to cause conductivity modulation in the drift layer to reduce the resistance of the drift layer
Data Source
AI summary
An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.