Trench IGFET Shield Electrode Structure for Capacitance Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in forming insulated gate field effect transistor (IGFET) devices with complex process steps, thick oxidation layers, and deep trenches, which hinder manufacturability and device performance.
Innovation Solution
A scalable, self-aligned process using a disposable dielectric stack and spacer structures to form trench insulated gate and shield electrode portions, enabling shallower trench structures, thinner epitaxial layers, and gate silicide enhancement regions without requiring expensive capital investments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick oxidation layers are used to form self-aligned source and body contacts, then self-alignment is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent uses a disposable sacrificial oxide layer that is intentionally grown and then completely removed after serving its temporary purpose of defining contact regions. This sacrificial layer enables self-aligned contact formation without requiring thick permanent oxidation layers, thereby reducing process complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary oxidation to form a sacrificial oxide layer that defines the contact regions before the actual contact formation process. This preliminary action establishes the self-aligned geometry early in the process, allowing subsequent steps to proceed with simpler, less complex operations.
2Manufacturing precision
If thick oxidation layers are used, then self-aligned contacts are formed, but gate silicide structures cannot be used
Solution Approach 1:
The sacrificial oxide layer is grown temporarily to define contact regions, then completely removed to expose the substrate for gate silicide formation. This disposable approach enables both self-aligned contacts and gate silicide structures to coexist in the final device, eliminating the mutual exclusivity imposed by thick permanent oxidation layers.
Solution Approach 2:
The oxidation process is segmented into a temporary sacrificial oxidation step followed by complete oxide removal, rather than using a single thick permanent oxidation layer. This segmentation allows the contact regions to be defined without permanently blocking the gate area for silicide formation.
3Reliability
If deeper trenches are used, then blocking voltage performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from vertical trench depth as the primary dimension for achieving blocking voltage to a combination of shallower trench depth and lateral shield electrode extension. By utilizing the lateral dimension more effectively, the device achieves equivalent or superior blocking voltage performance with reduced vertical complexity, making manufacturing easier and less costly.
Solution Approach 2:
The patent changes the geometric parameters of the shield electrode, extending it laterally beyond the gate region. This parameter change allows the device to achieve improved blocking voltage performance through increased lateral coverage rather than increased vertical depth, thereby reducing trench depth requirements and associated manufacturing complexity.
4Reliability
If tighter geometries are used, then field plate performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent employs spacer structures that are self-aligned to the gate and shield electrode regions, automatically defining the precise geometry of contact holes and other features. This self-service approach eliminates the need for complex photolithographic patterning steps to achieve tight geometries, as the spacers themselves serve as the alignment reference, thereby improving manufacturability while maintaining tight geometric tolerances.
Data Source
AI summary
In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions.