Trench-Isolated CMOS Wells for Thin-Wafer Leakage Control
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Solution Overview
Problem
Advanced semiconductor device assemblies face challenges in electrical isolation and leakage prevention between transistor well regions due to the thinning of CMOS wafers, which can lead to parasitic effects and latch-up risks, especially when deep well regions are ion-implanted in thinned substrates.
Innovation Solution
The implementation of fully trench isolated FETs in CMOS wafers for wafer-to-wafer bonding using dielectric layers, where deep trench isolation regions completely surround well regions, eliminating leakage currents and incorporating dedicated TAP cells to prevent latch-up, thereby avoiding the complexity of triple well isolation processes and enhancing packaging density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If CMOS wafers are thinned for wafer-to-wafer bonding, then packaging density is improved, but electrical isolation between well regions deteriorates leading to leakage currents and latch-up risks
Solution Approach 1:
The patent divides the isolation structure into multiple segments: shallow trench isolation (STI) regions at the surface level and deep trench isolation (DTI) regions extending below the active regions. This segmented approach provides comprehensive electrical isolation even when the wafer is thinned, as the DTI regions remain below the bonding interface to prevent leakage currents between adjacent transistor cell units.
Solution Approach 2:
The patent extends isolation from a two-dimensional surface structure (STI) into the third dimension (depth) by forming DTI regions that penetrate below the active regions. This vertical extension ensures that when the wafer is thinned for bonding, the deep trenches continue to provide electrical isolation from the bonding interface, preventing latch-up and leakage currents.
2Reliability
If deep trench isolation regions are formed to extend below transistor active regions, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the isolation function into a unified DTI structure that simultaneously achieves electrical isolation between adjacent transistor cell units and provides a bonding interface for wafer-to-wafer assembly. The DTI regions serve dual purposes: preventing leakage currents and enabling reliable bonding, thereby reducing the need for separate isolation and bonding preparation structures.
3Reliability
If traditional triple well isolation processes are used, then electrical isolation is achieved, but area efficiency deteriorates reducing packaging density
Solution Approach 1:
The patent extracts the essential isolation function from the complex triple well process and implements it through simpler DTI structures. By using deep trench isolation with dielectric filling, the patent achieves the same electrical isolation效果 as triple well but with reduced area overhead, allowing higher packaging density in the semiconductor device assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides superior electrical isolation and prevents leakage currents between well regions, reducing parasitic capacitance and latch-up risks, while allowing for thinner CMOS devices and higher packaging density through the use of dielectric isolation, which is more area-efficient than traditional triple well schemes.
Implementation Method 1
deep trench isolation regions filled by thick dielectric layers that extend below the transistor active regions in order to prevent leakage currents
Implementation Method 2
Conventional technologies including direct bonding and fusion bonding can be used to bond the CMOS wafer and one or more memory array wafers to form the semiconductor device assemblies
Data Source
AI summary
A semiconductor device including a complementary metal-oxide-semiconductor (CMOS) device that includes a P-Well region including a P-Well, a first shallow trench isolation (STI) region that is disposed on a frontside surface of the CMOS device and above the P-Well, and a first deep trench isolation (DTI) region that is disposed under the first STI region and that extends to a backside surface of the CMOS device, the first DTI region completely surrounding the P-Well, and a N-Well region adjacent to the P-Well region, the N-Well region including a N-Well, a second STI region disposed on the frontside surface of the CMOS device and above the N-Well, and a second DTI region that is disposed under the second STI region and that extends to the backside of the CMOS device, the second DTI region completely surrounding the N-Well; and a secondary device bonded to the CMOS device.