Trench Isolation Structure to Prevent Gate Bridge Defects
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Solution Overview
Problem
Existing semiconductor devices face issues with bridge defects between neighboring gate electrodes due to conductive materials remaining in dents formed between the liner pattern and the trench sidewall, and high electric field concentrations at the edge of the active region.
Innovation Solution
The semiconductor device is designed with a trench isolation structure where the inner wall oxide layer pattern and liner pattern are conformally formed without a step difference, and the top surfaces of these patterns are lower than the substrate surface, exposing the upper sidewall of the trench, thereby preventing the formation of dents and reducing the risk of bridge defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the liner pattern is formed conformally on the inner wall oxide layer pattern, then the isolation structure provides good electrical isolation, but dents are formed between the liner pattern and trench sidewall causing bridge defects
Solution Approach 1:
The patent applies preliminary action by forming the inner wall oxide layer pattern on the trench sidewall before forming the liner pattern. This pre-formed oxide layer serves as a foundation that prevents dent formation when the liner pattern is subsequently deposited conformally, thereby eliminating the source of bridge defects while maintaining electrical isolation functionality.
Solution Approach 2:
The inner wall oxide layer pattern acts as an intermediary between the trench sidewall and the liner pattern. This intermediate layer mediates the interaction between the substrate and the liner material, preventing direct contact that would cause dents and bridge defects, while still allowing the liner pattern to provide its electrical isolation function.
2Ease of manufacture
If the top surface of the isolation structure is flush with the substrate surface, then the manufacturing process is simpler, but electric field concentrations occur at the edge of the active region
Solution Approach 1:
The patent applies local quality by creating a non-uniform top surface profile where the isolation structure's top surface is positioned at different heights in different regions. Specifically, the top surface is lower than the substrate surface at certain locations, which locally modifies the electric field distribution to reduce concentration at the active region edges while maintaining overall manufacturing feasibility.
Solution Approach 2:
The patent introduces height variation as an additional dimensional parameter in the isolation structure design. By controlling the top surface to be at different elevations relative to the substrate surface, the solution transforms a two-dimensional planar structure into a three-dimensional profiled structure, thereby addressing electric field concentration issues through vertical dimension control.
Data Source
AI summary
A semiconductor device including a substrate including a trench; an isolation structure including an inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern stacked in the trench; and a gate structure on the substrate and the isolation structure, wherein the inner wall oxide layer pattern and the liner pattern are conformally formed on a surface of the trench, a top surface of the inner wall oxide layer pattern is lower than an upper surface of the substrate, and a boundary between an upper surface of the inner wall oxide layer pattern and an upper surface of the liner pattern has no step difference.