Trench Isolation Flatness via Dual Insulator CMP
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Solution Overview
Problem
Trench isolation methods in semiconductor manufacturing result in steps between active regions and insulating films, leading to electrical field concentration and adverse effects on transistor properties, particularly as devices miniaturize, due to incomplete removal of insulating films during the flattening process.
Innovation Solution
A method involving the use of two insulating films with no difference in polishing rate for chemical mechanical polishing, where a first insulating film serves as a mask to form trench regions and a second insulating film is embedded with a recess and protrusion, followed by removal steps to reduce the step height to 20 nm or less, using a CMP method with a slurry containing abrasive particles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If trench isolation method is used to form narrow and deep trench regions, then the area occupied by element isolation regions becomes small and active regions can be secured, but steps are formed between active regions and insulating films causing electrical field concentration
Solution Approach 1:
A pad oxide film is formed on the semiconductor substrate before trench formation. This preliminary oxide layer serves as a foundation that, when planarized later, helps eliminate surface steps and achieve better flatness in the final insulating film structure.
Solution Approach 2:
The patent employs chemical mechanical polishing (CMP) to change the surface topology parameter of the insulating film. By controlling the polishing process, the step height between active regions and insulating films is reduced to 20 nm or less, transforming a rough surface with electrical field concentration into a flat surface suitable for miniaturized devices.
2Reliability
If LOCOS method is used for electrical isolation, then the quality of oxide film is excellent and fewer stress problems occur, but the area occupied by element isolation regions becomes large
Solution Approach 1:
The patent replaces the thermal oxidation process of LOCOS with a deposition-based trench isolation method. Instead of growing oxide in-situ on the substrate surface, insulating films are deposited to fill etched trenches, then planarized using CMP. This substitution allows for better area utilization while maintaining film quality through controlled deposition and polishing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes steps between active and insulating regions, reducing electrical field concentration and enhancing transistor properties by maintaining flatness until the gate electrode formation, thus improving the overall performance and miniaturization capabilities of semiconductor devices.
Implementation Method 1
removing the first insulating film and the second insulating film in accordance with a chemical mechanical polishing method so that the step formed of the recess and protrusion is reduced to 20 nm or less
Implementation Method 2
In the second removal step, a slurry including 0.2 to 0.6% by weight of abrasive particles is used
Data Source
AI summary
A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating film to be used as a mask for forming a trench region directly above a semiconductor substrate; forming the trench region on the semiconductor substrate using the mask; forming a second insulating film directly above the semiconductor substrate which includes the trench region and the first insulating film so that the second insulating film has a recess above the trench region and a protrusion above the first insulating film; removing the protrusion down to the bottom of the recess as a first removal step; and removing the first insulating film and the second insulating film in accordance with a chemical mechanical polishing method so that the step formed of the recess and protrusion is reduced to 20 nm or less as a second removal step.