Trench Isolation Formation with Dual-Depth Etching and Planarization
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Solution Overview
Problem
The conventional method of forming shallow trench isolation (STI) and deep trench isolation (DTI) in semiconductor devices requires sequential processes, leading to a lengthy and inefficient fabrication process.
Innovation Solution
A method where a first etching process forms shallow trenches using a first mask layer, followed by filling with a dielectric layer, patterning to create a second mask layer for a second etching process to form deep trenches, with both trench types being filled with dielectric material and planarized in a single CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sequential processes are used to form STI and DTI structures separately, then each trench type can be formed with proper depth and isolation, but the fabrication process becomes lengthy and inefficient
Solution Approach 1:
The patent performs the STI formation process first, filling shallow trenches with dielectric material and planarizing the surface before forming DTI. This preliminary action allows the DTI etching process to start from a flat surface, ensuring proper etch depth control while enabling both trench types to be formed in an integrated sequence rather than completely separate processes, thus improving overall fabrication efficiency
Solution Approach 2:
The patent divides the trench isolation formation into segmented stages: first forming STI in shallow trenches, then forming DTI in deeper trenches. By segmenting the process into controlled stages with intermediate planarization, each trench type achieves its required depth precision while the overall process flows continuously, avoiding the inefficiency of fully sequential independent processes
2Manufacturing precision
If multiple sequential trench formation processes are used, then different depth requirements for STI and DTI are met, but the number of process steps increases
Solution Approach 1:
The patent merges the STI and DTI formation processes into an integrated sequence where STI is formed first, followed by DTI formation using the STI structure itself as part of the process. The dielectric layer filling and CMP planarization steps are combined in a unified workflow, reducing the number of independent process modules while maintaining precise depth control for both trench types
3Manufacturing precision
If STI and DTI are formed in separate sequential processes, then each isolation structure can be optimized independently, but overall processing time increases
Solution Approach 1:
The STI formation is performed as a preliminary action before DTI formation, with the dielectric layer being filled and planarized in advance. This preliminary STI structure then serves as a foundation for the subsequent DTI etching process, allowing both isolation structures to be optimized independently in terms of their respective dielectric materials and etch parameters, while the overall processing time is reduced through this integrated sequential approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process and improves planarization quality by allowing both STI and DTI to be formed ahead of the CMP process, reducing overall processing time and complexity.
Implementation Method 1
A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure... a second etching process to form a deep trench structure
Implementation Method 2
forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure... a dielectric material is applied to fill the deep trench structure
Implementation Method 3
Both trench types being filled with dielectric material and planarized in a single CMP process
Data Source
AI summary
A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.