Multi-layer Trench Isolation for 10nm FinFET Density
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to the 10 nanometer node or smaller, due to variability in conventional methods, which limits the integration of new technologies and the fabrication of functional components for future technology nodes.
Innovation Solution
The implementation of pitch quartering and trench isolation techniques, including multi-layer trench isolation structures and fin trim processes, to enhance the density and performance of integrated circuit structures, allowing for precise control of doping and stress induction in semiconductor fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple distinct stages including pitch quartering (dividing the pattern into quarters) and multi-layer trench isolation formation. This segmentation allows each stage to be optimized independently for precision while managing overall process complexity through modular organization of fabrication steps.
Solution Approach 2:
The patent introduces multi-layer trench isolation structures that add vertical dimensionality to the fabrication process. By creating isolation trenches at different depths and layers, the process achieves higher precision in controlling fin dimensions while managing complexity through three-dimensional structural organization rather than relying solely on planar processing.
2Manufacturing precision
If new technologies are integrated to improve manufacturing precision, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Pitch quartering and trench isolation structures are formed as preliminary actions before final fin patterning and device assembly. By pre-establishing precise reference structures and isolation frameworks in advance, the subsequent fabrication steps can achieve higher fin dimension control without proportionally increasing overall process integration complexity.
Solution Approach 2:
The multi-layer trench isolation structures serve as intermediary elements between the substrate and the active device regions. These isolation structures mediate the interaction between different fabrication stages, enabling precise fin dimension control by providing stable reference planes and mechanical support, thereby managing process integration complexity through the use of intermediate structural elements.
3Quantity of substance
If feature size is reduced to increase device density, then device density improves, but manufacturing precision deteriorates due to variability
Solution Approach 1:
Pitch quartering divides the original pitch into four smaller segments through multiple patterning steps. This segmentation approach enables the fabrication of higher density transistor arrays with improved feature size control by breaking down the challenging single-step patterning into manageable sequential steps, each with better process control and reduced variability.
Solution Approach 2:
Multi-layer trench isolation structures provide vertical separation and support that enables higher transistor density in the planar direction while maintaining manufacturing precision. By utilizing the vertical dimension for isolation and structural support, the process can pack more devices per unit area without proportionally reducing feature size control capability.
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.