Trench Isolation With Floating Buried Layer For Semiconductor Reliability
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Solution Overview
Problem
Existing semiconductor isolation schemes, such as junction isolation and SOI technologies, face challenges including increased chip size, high capacitance, thermal dissipation issues, and susceptibility to parasitic currents, which affect the robustness and reliability of smart power devices.
Innovation Solution
A self-isolating bulk semiconductor substrate with a floating buried doped region and trench isolation structure, where the floating buried doped region abuts the trench isolation structure without direct ohmic contact, and additional isolation devices are used to control parasitic currents and leakage paths, enhancing electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If junction isolation schemes are used, then electrical isolation is achieved, but chip size increases and capacitance increases
Solution Approach 1:
The patent transitions from lateral junction isolation to vertical trench isolation, moving the isolation mechanism into the depth dimension. Trench isolation structures extend vertically into the substrate, providing electrical isolation through the third dimension rather than requiring increased lateral spacing between devices.
Solution Approach 2:
The patent applies different isolation mechanisms to different regions: trench isolation for vertical substrate isolation and selective junction isolation only where needed for lateral device separation. This localized approach reduces overall chip area while maintaining necessary electrical isolation.
2Reliability
If junction isolation schemes are used, then electrical isolation is achieved, but capacitance increases
Solution Approach 1:
By using vertical trench isolation instead of lateral junction isolation, the patent reduces the overlapping area between doped regions and isolation structures, thereby reducing parasitic capacitance while maintaining electrical isolation.
3Area of stationary object
If SOI technology is used, then chip size is reduced, but thermal dissipation deteriorates and manufacturing cost increases
Solution Approach 1:
The patent uses a composite isolation structure combining semiconductor material trenches with dielectric filling materials. This allows vertical isolation similar to SOI while maintaining thermal conduction paths through the semiconductor substrate, improving thermal dissipation compared to full SOI structures.
Solution Approach 2:
The patent applies trench isolation only in specific regions where substrate isolation is needed, rather than using full SOI technology across the entire chip. This localized approach reduces manufacturing cost while maintaining thermal dissipation benefits of bulk substrate in non-isolated regions.
Data Source
AI summary
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.