Trench Isolation Gate Dielectric for High-Voltage FETs
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Solution Overview
Problem
Conventional semiconductor devices using bulk silicon substrates face limitations in power efficiency and defect density, while existing SOI technologies like SIMOX processes have thickness uniformity issues and high defect densities.
Innovation Solution
The use of a silicon-on-insulator (SOI) substrate with a trench dielectric layer extending to the buried oxide layer, which serves as a gate dielectric for field effect transistors (FETs), enabling the formation of inversion layers and supporting high-voltage biases, thereby enhancing the gate voltage rating and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SIMOX process is used to produce SOI substrates, then oxygen implantation creates a buried oxide layer, but thickness uniformity deteriorates and defect density increases
Solution Approach 1:
The patent extracts the problematic SIMOX process step and replaces it with a wafer bonding approach. The buried oxide layer is formed by bonding a separate oxide layer to the silicon substrate, rather than implanting oxygen into the substrate. This extraction of the problematic process step eliminates the thickness uniformity and defect density issues associated with SIMOX while maintaining the SOI structure's beneficial properties.
2Ease of manufacture
If conventional bulk silicon substrates are used, then manufacturing is simpler, but power efficiency deteriorates and defect density increases
Solution Approach 1:
The patent segments the substrate into distinct functional layers: a silicon device layer, a buried oxide layer, and a handle layer. This segmentation creates the SOI structure that provides both the manufacturing simplicity of bonded layers and the superior power efficiency and defect reduction of isolated device regions. The trench isolation further segments individual devices, enhancing power efficiency while maintaining manufacturability.
Solution Approach 2:
The patent employs composite material structure by combining silicon and oxide layers in a bonded configuration. This composite SOI substrate integrates the electrical properties of silicon with the insulating properties of the buried oxide, achieving both ease of manufacture through standard bonding processes and superior device performance including power efficiency and reduced defect density.
3Reliability
If trench dielectric layer extends to BOX layer to serve as gate dielectric, then gate voltage rating improves to ±150 V, but device structure complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the trench isolation structure to serve dual purposes: electrical isolation between devices and gate dielectric for high-voltage operation. The trench dielectric layer that would normally only provide isolation now also functions as the gate dielectric, enabling ±150 V operation without requiring a separate gate oxide layer. This eliminates redundant structures and reduces overall device complexity despite the enhanced functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the creation of high-voltage tolerant FETs with improved thickness uniformity and reduced defect density, suitable for cost-sensitive applications such as analog multiplexers, current-sense monitors, and high-voltage sensors, with a gate voltage rating of at least ±150 V.
Implementation Method 1
A gate region having a gate contact is separated from the inner portion by the trench dielectric
Implementation Method 2
enabling the formation of inversion layers and supporting high-voltage biases
Implementation Method 3
a wafer bonding process to achieve a thinner device layer that may have better thickness uniformity and lower defect density
Implementation Method 4
a SIMOX (Separation by IMplantation of Oxygen) process which uses a very high dose oxygen implant process followed by a high temperature anneal
Implementation Method 5
followed by a high temperature anneal
Data Source
AI summary
A semiconductor device includes a Silicon-on-Insulator (SOI) substrate including a top device layer, a buried oxide (BOX) layer, and a bottom handle portion. A filled trench is lined with a trench dielectric layer that extends to at least the BOX layer, defining an inner and an outer portion of the device layer. A field effect transistor (FET) includes an inner portion, a source region having a source contact thereto and a drain region having a drain contact thereto, each doped a first doping type. A gate region has a gate contact that is separated from the inner portion by the trench dielectric. The source and drain region are separated by a body region doped a second doping type having a body contact.