Trench Isolation Layer with Micro Trenches and Graded Liner
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Solution Overview
Problem
As semiconductor devices become more integrated, the isolation layers in semiconductor devices face challenges such as voids and seams when design rules are reduced to 30 nanometers or less, leading to stress and crystalline defects due to impurities in spin on dielectric (SOD) or flowable oxide layers, which can cause warping of the wafer.
Innovation Solution
A semiconductor device with a trench isolation layer comprising a nitride liner insulation layer, a high density plasma (HDP) oxide first isolating layer, and an ozone tetra-ethyl-ortho-silicate (O3 TEOS) second isolating layer, where the liner insulation layer's thickness gradually increases towards the bottom of the trench, and micro trenches are formed at the inner corners, minimizing stress and impurity-related issues by avoiding the use of SOD or flowable oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If spin on dielectric (SOD) layer or flowable oxide layer is used to form isolation layers, then excellent isolation layers without voids and seams can be obtained, but impurities such as carbon hydride (CH) or nitrogen hydride (NH) are introduced, causing the layer to shrink and increase in density, generating stress and crystalline defects in the substrate
Solution Approach 1:
The patent extracts and eliminates the problematic SOD or flowable oxide layers that contain impurities (CH, NH) from the isolation layer formation process. Instead, it uses a trench isolation structure filled with inert gas or vacuum, removing the source of impurities while maintaining the void-free, seam-free isolation quality.
Solution Approach 2:
The patent changes the material composition parameter of the isolation layer from organic-containing materials (SOD, flowable oxide) to inorganic materials (oxide, nitride) filled with inert gas or vacuum. This parameter change eliminates impurity introduction while maintaining effective isolation.
2Manufacturing precision
If the isolation layer volume is reduced after impurity removal, then the isolation layer becomes denser, but stress is generated causing wafer warping and crystalline defects
Solution Approach 1:
The patent applies a liner insulation layer to the trench walls before filling with inert gas or vacuum. This liner layer acts as a cushioning element that prevents stress concentration and protects the substrate from warping and crystalline defects while allowing the isolation layer to achieve high density.
Solution Approach 2:
The patent creates a composite isolation structure combining the liner insulation layer (oxide or nitride) with the inert gas or vacuum fill. This composite structure achieves both high density and low stress, preventing substrate warping while maintaining effective isolation.
3Productivity
If design rules are reduced to 30 nanometers or less, then higher integration is achieved, but voids and seams are formed in shallow trench isolation (STI) layers
Solution Approach 1:
The patent transitions from planar STI to a three-dimensional trench isolation structure with vertical walls. By etching deep trenches and filling them with inert gas or vacuum, the structure maintains effective isolation at reduced design rules without forming voids or seams, as the vertical configuration allows complete filling without the lateral flow limitations of planar structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively forms a reliable trench isolation layer without voids or seams, reducing stress and preventing crystalline defects, thereby enhancing the reliability and integrity of semiconductor devices by densifying the O3 TEOS layer through an annealing process without generating impurities like carbon hydride or nitrogen hydride.
Implementation Method 1
a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The first isolating insulation layer may include a high density plasma (HDP) oxide layer.
Implementation Method 2
densifying the O3 TEOS layer through an annealing process without generating impurities like carbon hydride or nitrogen hydride
Data Source
AI summary
Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.