Trench Isolation Routing Electrodes for Dense Semiconductor Interconnects

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Solution Overview

Problem

The challenge of connecting multiple semiconductor devices among circuits becomes increasingly complex and costly as more stacks of circuits are interconnected, particularly due to the need for additional metal routing paths which can interfere with device performance and increase parasitic capacitances.

Innovation Solution

A routing electrode layer is deposited in the recess of trench isolations to facilitate chip-level metal routing, allowing for additional interconnection areas without interfering with active device regions, and can be integrated with planar or 3D transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional metal routing paths are used to connect multiple semiconductor devices, then interconnection capability is improved, but parasitic capacitances increase and device performance deteriorates

Engineering Contradiction:
Improveinterconnection capabilityVSAvoidparasitic capacitances
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent utilizes the vertical dimension by forming routing electrode layers within recesses of trench isolation structures. Instead of adding more horizontal metal routing layers, the invention creates conductive paths by etching recesses into the trench isolation and filling them with routing electrodes, thereby achieving additional interconnection capability in the vertical dimension without increasing parasitic capacitances from additional planar metal layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If more stacks of circuits are interconnected, then circuit integration is improved, but fabrication complexity and cost increase

Engineering Contradiction:
Improvecircuit integrationVSAvoidfabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the formation of routing electrodes with the existing trench isolation fabrication process. The routing electrode layer is formed within the trench isolation recesses using the same etching and filling steps already required for isolation structures, thereby integrating additional interconnection functionality without proportionally increasing fabrication complexity or cost

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If metal routing paths are added to connect multiple devices, then interconnection capability is improved, but manufacturing cost increases

Engineering Contradiction:
Improveinterconnection capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The trench isolation structure serves multiple functions: it provides electrical isolation between devices and simultaneously houses the routing electrode layers for interconnection. This multi-functionality allows the same structural element to deliver both isolation and routing capabilities, avoiding the need for separate dedicated routing structures and thereby reducing manufacturing cost while maintaining improved interconnection capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12432927B2Semiconductor devices, systems, and methods for forming the same
Publication Date: 2025.09.30 YANGTZE MEMORY TECH CO LTD
  • US12432927B2 patent drawing
  • US12432927B2 patent drawing
  • US12432927B2 patent drawing

AI summary

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.