Trench Isolation Structures for Semiconductor Device Manufacturing
Solution Overview
Problem
Existing methods for isolating regions in semiconductor devices, such as those integrating high power and high voltage devices with logic or analog circuits, face challenges like parasitic effects, complex processing steps, and incompatibility with standard CMOS processes, leading to increased costs and susceptibility to process variations.
Innovation Solution
A method involving a substrate with a buried layer of a second semiconductor material, a device layer of a third semiconductor material, and forming trench isolation structures that are partially filled with insulator to expose the buried layer, allowing for selective etching to create isolated regions without the need for multiple trench etch steps, thus simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple trench etch steps are used to form isolation structures, then isolation effectiveness is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before trench etching that pre-defines the isolation region geometry. This mandrel serves as a template that guides subsequent single-step trench formation, eliminating the need for multiple patterning and etch steps while maintaining precise isolation effectiveness.
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element that mediates between the desired isolation pattern and the final trench structure. This intermediate mandrel enables single-step trench formation by acting as a physical guide, thereby reducing processing complexity while achieving effective isolation.
2Reliability
If conventional CMOS processes are used with buried oxide layers, then device isolation is improved, but parasitic effects increase
Solution Approach 1:
The patent applies local quality by implementing isolation structures only in specific regions where high voltage devices are located, rather than using blanket buried oxide layers across the entire substrate. This localized approach provides necessary isolation for high voltage devices while minimizing parasitic effects in logic circuit regions.
Solution Approach 2:
The patent segments the substrate into isolated high voltage device regions and non-isolated logic circuit regions using targeted trench isolation structures. This segmentation allows different electrical characteristics in different areas, achieving isolation where needed while avoiding parasitic effects in other areas.
3Reliability
If deep trench isolation structures are formed to remove parasitic effects, then isolation effectiveness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by designing the mandrel structure to automatically define the trench depth and geometry through self-aligned processes. The mandrel's physical dimensions directly determine the isolation trench characteristics, eliminating the need for complex depth control mechanisms and reducing sensitivity to process variations.
Solution Approach 2:
The mandrel structure is formed in advance with precisely controlled dimensions that pre-determine the final isolation trench geometry. This preliminary definition of isolation region boundaries through the mandrel reduces the precision requirements for subsequent trench etching steps.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.