Trench Isolation Regions Maintain Channel Stress in SOI Devices
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Solution Overview
Problem
Current semiconductor devices using SOI technology face limitations in enhancing channel stress for improved performance, particularly in achieving higher electron mobility and maintaining strain in active regions.
Innovation Solution
A method involving the formation of laterally adjacent active regions in a SOI wafer, with a stress-inducing layer above one active region and trench isolation regions to freeze the stress, utilizing lattice mismatch and high temperature anneal to maintain strain, and forming gate stacks and raised source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress inducing layer is formed above an active region to impart stress, then electron mobility is enhanced, but the stress relaxes when the stress inducing layer is removed
Solution Approach 1:
Trench isolation regions are formed before the stress inducing layer is removed, creating a structural framework that will subsequently maintain the stress state. The trenches are etched and filled with isolation material to establish boundaries that prevent stress relaxation before the stress inducing layer completes its function
Solution Approach 2:
Trench isolation regions serve as intermediary structures that mediate between the stress inducing layer and the active region. These isolation regions extend into the substrate and physically constrain the active region, preventing stress relaxation while allowing the stress inducing layer to be removed after imparting the desired stress
2Stability of the object's composition
If trench isolation regions are formed to maintain stress, then channel stress is preserved, but device structure becomes more complex
Solution Approach 1:
The trench isolation regions perform multiple functions simultaneously: they provide electrical isolation between adjacent devices, mechanically constrain the active region to maintain channel stress, and serve as structural anchors that prevent stress relaxation. This multi-functionality reduces the need for additional dedicated stress-maintenance structures
Solution Approach 2:
The isolation structure is merged with the stress-maintenance function by extending the trench isolation regions into the substrate beneath the active region. This integration combines what would otherwise be separate functions (isolation and stress maintenance) into a single unified structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively enhances electron mobility and maintains the active region in a strained state, improving device performance by using lattice mismatch-induced stress and trench isolation to prevent strain relaxation.
Implementation Method 1
The stress is based on a lattice mismatch at an interface between the stress inducing layer and the first active region
Implementation Method 2
The trench isolation regions advantageously hold or freeze the first active region in a stressed state
Implementation Method 3
To densify the trench isolation regions, a high temperature anneal may be performed after the stress inducing layer has been removed
Data Source
AI summary
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.