Trench Isolation Layer Formation with Tapered Conductive Patterns
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Solution Overview
Problem
In high-integrated semiconductor devices, the narrow and deep trenches pose challenges in completely filling the trench with a high density plasma (HDP) oxide layer without voids, leading to shifting cycling threshold voltage and overhang formation, which is exacerbated by the spin on glass (SOG) method.
Innovation Solution
A method involving the formation of conductive layer patterns with a narrower upper portion and a spacer on a semiconductor substrate, followed by repeated deposition and wet etching processes to fill the trench with a high density plasma oxide layer, ensuring the thickness on the side wall and preventing overhangs, thereby securing the oxide layer thickness and improving threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of HDP oxide layer is increased to secure side wall thickness, then the threshold voltage stability is improved, but overhang forms on the upper area of the trench
Solution Approach 1:
The conductive layer pattern is divided into upper and lower portions with different widths, creating a tapered structure that segments the trench filling process. This segmentation allows the oxide layer to be deposited without forming overhangs while maintaining sufficient side wall thickness
Solution Approach 2:
The conductive layer pattern uses asymmetric width distribution, with the upper portion being narrower than the lower portion. This asymmetric design prevents overhang formation during oxide layer deposition while ensuring adequate side wall coverage for threshold voltage stability
2Reliability
If HDP oxide layer is used to fill the trench, then the isolation performance is improved, but voids remain in narrow and deep trenches
Solution Approach 1:
The trench filling process is segmented into multiple deposition cycles separated by etching steps. Each cycle deposits a portion of the oxide layer, and the etching step removes overhangs to open up the trench for subsequent complete filling
Solution Approach 2:
The process employs periodic alternation between oxide layer deposition and etching steps. This periodic action progressively fills the trench while maintaining openness for complete material penetration, eliminating voids while preserving isolation performance
3Manufacturing precision
If SOG method is used to fill the trench, then the void-free filling is achieved, but the cycling threshold voltage shifts
Solution Approach 1:
The conductive layer pattern with tapered geometry serves as an intermediary structure that mediates between the filling requirement and the electrical performance requirement. It enables HDP oxide deposition to achieve both complete filling and adequate side wall thickness without the threshold voltage shifting problem
Solution Approach 2:
The process changes the geometric parameters of the conductive layer pattern, specifically the width ratio between upper and lower portions. This parameter change enables the HDP oxide layer to conformally coat the side walls with sufficient thickness while preventing overhang formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively secures the thickness of the oxide layer on the side wall, prevents overhangs, and reduces the shift in cycling threshold voltage, ensuring complete trench filling without voids and minimizing interference phenomena.
Implementation Method 1
forming an insulating layer to filling a portion of the trench with the insulating layer; the insulating layer is formed of a high density plasma oxide layer
Implementation Method 2
performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns; the etching process preferably is a wet etching process
Data Source
AI summary
The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns being narrower than that of a lower portion; forming a trench between the conductive layer patterns on the semiconductor substrate; forming an insulating layer to fill a portion of the trench with the insulating layer; and performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns. Here, the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer.