Shallow Trench Isolation Structure Without Void Pinch-Off
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Solution Overview
Problem
Current semiconductor isolation technologies face challenges in forming high aspect ratio trench isolation structures without voids, which can lead to reduced effectiveness and increased defects due to pinch-off or collapse of insulation material during deposition and etching processes.
Innovation Solution
The method involves forming multiple electrical insulator layers in a trench with controlled deposition and etching rates, using techniques like sputter-etching and plasma deposition, to ensure that insulation material accumulates faster at the bottom than on the sides, preventing void formation and maintaining a high aspect ratio without pinch-off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition and etching processes are used to form high aspect ratio trench isolation structures, then the trench can be formed with sufficient depth and width, but voids form due to pinch-off or collapse of insulation material
Solution Approach 1:
The patent applies periodic action by implementing multiple iterative cycles of deposition and etching processes. Each cycle deposits insulation material and then selectively removes it, with the deposition rate being greater than the etching rate. This periodic repetition allows gradual accumulation of material that prevents void formation while achieving the required trench depth and isolation quality.
Solution Approach 2:
The patent changes the deposition rate parameter to be greater than the etching rate parameter, which is a fundamental parameter change from conventional processes where etching rate typically exceeds deposition rate. This parameter inversion allows material accumulation that prevents pinch-off and collapse, thereby forming void-free high aspect ratio trench isolation structures with improved reliability.
2Productivity
If insulation material is deposited at conventional rates, then the deposition process is efficient, but pinch-off or collapse occurs leading to void formation
Solution Approach 1:
The periodic deposition-etching cycles allow efficient material deposition while preventing defects. Each deposition phase accumulates material at a rate greater than etching, and the subsequent etching phase selectively removes excess material, maintaining structural integrity throughout the efficient deposition process.
Solution Approach 2:
The process incorporates feedback by using the etching step to monitor and control material accumulation. The etching rate serves as a reference against which deposition is measured, allowing real-time adjustment to maintain the critical condition that deposition rate exceeds etching rate, thereby preventing pinch-off while maintaining productivity.
3Reliability
If multiple electrical insulator layers are formed with controlled deposition and etching rates, then void formation is prevented, but the process complexity increases
Solution Approach 1:
The patent segments the isolation structure formation into multiple distinct electrical insulator layers, each formed by controlled deposition and etching cycles. This segmentation allows precise control over material accumulation in different regions of the trench, preventing void formation while organizing the complex process into manageable, repeatable units.
Solution Approach 2:
The patent systematically changes deposition and etching rate parameters across different layers and process cycles. By controlling these parameters to ensure deposition rate exceeds etching rate throughout the multiple layers, the process manages complexity through parameter standardization while achieving superior void-free isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of shallow trench isolation structures with minimal voids, enhancing the dielectric properties and reducing defects, thereby improving the performance and reliability of semiconductor devices.
Implementation Method 1
using techniques like sputter-etching and plasma deposition
Implementation Method 2
using techniques like sputter-etching and plasma deposition
Data Source
AI summary
A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.