Trench Semiconductor Layout for Lower Feedback Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with equal-depth gate and source trenches suffer from insufficient depletion layer spread, leading to inadequate short circuit withstand capability and high feedback capacitance, which limits their performance in diverse applications.
Innovation Solution
The semiconductor device features a trench source structure deeper than the gate trench, with a well region extending beyond the gate trench, allowing a depletion layer to spread further, thereby narrowing the current path and reducing feedback capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate trench and source trench are formed to substantially equal depths, then the manufacturing process is simplified, but the depletion layer cannot spread sufficiently and the short circuit withstand capability cannot be improved appropriately
Solution Approach 1:
The patent applies asymmetry by forming the source trench deeper than the gate trench. The source trench extends to a depth that allows the depletion layer to spread sufficiently from the deep well region, while the gate trench maintains an appropriate depth for gate control. This asymmetric depth configuration resolves the contradiction by enabling adequate depletion layer spread and short circuit withstand capability without requiring both trenches to be formed to the same depth, thus maintaining manufacturing simplicity while achieving reliability improvement.
Solution Approach 2:
The patent utilizes the depth dimension differently for the gate trench and source trench. By allowing the source trench to extend deeper into the semiconductor layer than the gate trench, the design creates a vertical dimension gradient that enables the depletion layer to spread effectively from the deep well region. This dimensional differentiation allows the depletion layer to reach the necessary extent for improving short circuit withstand capability while keeping the gate trench at an optimal depth for electrical control.
2Device complexity
If the gate trench and source trench are formed to substantially equal depths, then the device structure is simplified, but the feedback capacitance cannot be reduced appropriately
Solution Approach 1:
The patent applies asymmetry by configuring the source trench to be deeper than the gate trench. This asymmetric depth ratio (source trench depth/gate trench depth = 1.5-4.0) enables the depletion layer to spread effectively from the deep well region, thereby reducing the feedback capacitance between gate and drain. The simplified two-trench structure is maintained, avoiding complex multi-trench or three-dimensional structures, thus achieving low feedback capacitance with moderate structural complexity.
3Reliability
If the source trench is formed deeper than the gate trench, then the depletion layer can spread sufficiently to improve short circuit withstand capability, but the device structure becomes more complex
Solution Approach 1:
The patent applies parameter changes by optimizing the depth ratio between source trench and gate trench within a specific range (1.5-4.0). This parameter optimization ensures that the source trench is sufficiently deep to allow adequate depletion layer spread from the deep well region, improving short circuit withstand capability. Simultaneously, the depth ratio is constrained to prevent excessive complexity in the trench configuration, balancing reliability improvement with manageable device structure complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances short circuit withstand capability and reduces feedback capacitance, improving the reliability and switching speed of the semiconductor device.
Implementation Method 1
a depletion layer cannot be spread sufficiently from a boundary region between the semiconductor layer and the deep well region
Data Source
AI summary
A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.