Trench Semiconductor Layout for Low On-Resistance Switching

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Solution Overview

Problem

Semiconductor devices face challenges in reducing switching loss while minimizing on-resistance, as densely arranged connection regions increase on-resistance and recovery current density, leading to higher temperatures and increased switching loss.

Innovation Solution

A semiconductor device design with trenches on the substrate, a gate insulating film, and a gate electrode, featuring an element region with outer side portions and a central portion, where the interval between connection regions is greater in the outer side portions, reducing on-resistance and switching loss by allowing fewer holes to accumulate during forward biasing and providing a wider path for main current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If connection regions are densely arranged to reduce on-resistance, then electrical resistance decreases, but switching loss and temperature rise increase due to high hole accumulation

Engineering Contradiction:
Improveon-resistanceVSAvoidswitching loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by differentiating the interval between connection regions in different areas of the semiconductor device. Specifically, the interval between connection regions is set to be larger in the outer side portions compared to the central portion. This local differentiation allows the outer regions to have lower hole accumulation and reduced switching loss, while the central region maintains smaller intervals for lower on-resistance, thus resolving the contradiction between reducing on-resistance and reducing switching loss.

Inventive Principle:
Principle #3Local quality

2Reliability

If connection regions are densely arranged, then on-resistance is reduced, but temperature rise increases due to heat generation

Engineering Contradiction:
Improveon-resistanceVSAvoidtemperature rise
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent implements local quality by varying the spacing of connection regions across different zones. In the outer side portions, larger intervals between connection regions reduce heat generation and temperature rise, while in the central portion, smaller intervals maintain low on-resistance. This spatially differentiated arrangement allows the device to achieve both low on-resistance and controlled temperature rise simultaneously.

Inventive Principle:
Principle #3Local quality

3Loss of energy

If connection regions are spaced further apart, then switching loss is reduced, but on-resistance increases

Engineering Contradiction:
Improveswitching lossVSAvoidon-resistance
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent resolves this contradiction by applying local quality through non-uniform spacing of connection regions. The outer side portions have larger intervals between connection regions, which reduces switching loss in those areas. Meanwhile, the central portion maintains smaller intervals to keep on-resistance low. This localized differentiation allows each region to be optimized for its specific functional requirements.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces on-resistance and switching loss by optimizing the arrangement of connection regions, minimizing hole accumulation, and enhancing heat dissipation, thereby suppressing temperature rise and maintaining low switching loss.

Implementation Method 1

a gate insulating film covering an inner surface of each trench, and a gate electrode disposed in the trench and separated from the semiconductor substrate by the gate insulating film

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

The connection regions connect the body region and the bottom region, extend in the first direction, and are arranged at intervals in the second direction

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20230290849A1Semiconductor device
Publication Date: 2023.09.14 DENSO CORP
  • US20230290849A1 patent drawing
  • US20230290849A1 patent drawing
  • US20230290849A1 patent drawing

AI summary

In a semiconductor device, a semiconductor substrate has an element region and a peripheral region, and trenches are defined on an upper surface of the semiconductor substrate. The trenches extend in a first direction, and are arranged at intervals in a second direction. The element region includes an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and p-type connection regions. The bottom region is spaced from a bottom surface of the trenches. The connection regions connect the body region and the bottom region, extend in the first direction, and are arranged at intervals in the second direction. The element region has outer side portions and a central portion in the second direction. An interval between the connection regions in the second direction is greater in the outer side portion than in the central portion.