Trench Semiconductor Layout With Under-Gate Mesas for Photolithography
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Solution Overview
Problem
Conventional power semiconductor devices face challenges in photolithography processes due to topographical variations caused by trenches and mesas, leading to issues like resist pooling and streaking, which complicates the patterning of narrow features and increases on-resistance.
Innovation Solution
The introduction of under-gate mesas beneath the gate pad region, which are electrically isolated and have lower doping concentrations, helps to reduce topographical variations and enhance uniformity, thereby improving the application of photoresist and reducing resist streaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If trenches and mesas are used in the active region, then voltage blocking capability is improved, but topographical variations cause resist pooling and streaking during photolithography
Solution Approach 1:
The gate contact region is segmented into multiple under-gate mesas positioned beneath the gate pad, separating this region from the active region mesas. This segmentation allows the gate pad area to have a different topographical profile (flatter surface) compared to the active region, enabling better photolithography performance while preserving the voltage blocking function of the original mesas
Solution Approach 2:
Under-gate mesas act as an intermediary structure between the substrate and the gate pad. These mesas provide electrical isolation and create a more uniform surface topology in the gate contact region, mediating between the high-voltage blocking requirement (maintained by active region mesas) and the photolithography quality requirement (improved by the flatter gate region surface)
2Manufacturing precision
If under-gate mesas are introduced beneath the gate pad, then topographical uniformity is improved, but device structure complexity increases
Solution Approach 1:
Different mesa structures are applied to different regions of the device: the active region maintains high mesas for voltage blocking, while the gate contact region introduces under-gate mesas with different dimensions and electrical isolation characteristics to achieve local surface uniformity. This local differentiation resolves the topographical issues without requiring complete restructuring of the entire device
3Ease of manufacture
If conventional photolithography is used on topographically varied surfaces, then process simplicity is maintained, but on-resistance increases due to resist streaking
Solution Approach 1:
Under-gate mesas are formed in advance during the mesa formation process, before photolithography is applied to the gate contact region. This preliminary structuring of the gate region surface creates a more uniform topography that prevents resist pooling and streaking during subsequent photolithography steps, thereby maintaining process simplicity while improving electrical performance
Data Source
AI summary
A semiconductor device includes a semiconductor layer having an active region and a gate contact region adjacent the active region, a plurality of alternating mesa stripes and trenches in the active region, a gate contact pad on the semiconductor layer, and an under-gate mesa in the gate contact region beneath the gate contact pad. The semiconductor device may have a saw street at an outer periphery of the semiconductor layer, wherein a top surface of the saw street is at a same height above the substrate as top surfaces of the plurality of mesa stripes.