Trench Semiconductor Layout for Low Saturation Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with high-concentration N-type semiconductor layers face challenges in adjusting saturation voltage and reducing variations in characteristics such as threshold voltage.
Innovation Solution
The semiconductor device incorporates a specific layout of semiconductor layers and trench electrodes, including N-type and P-type semiconductor layers, and trench electrodes, which allows for the adjustment of saturation voltage and reduction of characteristic variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high-concentration N-type semiconductor layer is provided under the P-type channel region, then the saturation voltage can be reduced, but the characteristics such as threshold voltage of the MOS structure easily vary
Solution Approach 1:
The patent divides the semiconductor device into distinct functional regions: a first region with the high-concentration N-type semiconductor layer (N2) for low saturation voltage, and a second region without this layer for stable MOS characteristics. This spatial segmentation allows each region to optimize for its specific function without interference, resolving the contradiction between low saturation voltage and characteristic stability
Solution Approach 2:
The patent applies local quality by providing the high-concentration N-type semiconductor layer only in specific regions where low saturation voltage is needed, while maintaining different structural characteristics in other regions. This localized approach allows the device to achieve low saturation voltage in necessary areas without compromising the stability of MOS characteristics in sensitive areas
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.