Trench Structure LDMOS Reducing Area via Vertical Insulation
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Solution Overview
Problem
The challenge is to reduce the occupied area of LDMOS transistor devices in semiconductor substrates without compromising their performance, particularly in high-voltage environments, as miniaturization trends demand more efficient use of space.
Innovation Solution
The introduction of trench structures within the semiconductor device, where the first trench structure contacts and extends into the buried layer, substitutes for the conventional field oxide layer, utilizing vertical space to buffer high voltage signals and provide insulation, thereby reducing the horizontal occupied area and increasing substrate utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional field oxide layer is used for insulation and high voltage buffering, then device performance is maintained, but horizontal occupied area is large
Solution Approach 1:
The patent transitions from horizontal space utilization (field oxide layer extending laterally) to vertical space utilization (trench structures extending downward into the substrate). By etching trenches to contact the buried layer and filling them with insulating material, the device achieves the same insulation and voltage buffering functions while occupying less horizontal area, directly resolving the technical contradiction between area reduction and reliability maintenance.
2Reliability
If lateral diffused area with low dopant concentration is used, then high breakdown voltage is achieved, but device area increases
Solution Approach 1:
The patent replaces the lateral extension of low-dopant concentration regions with vertical trench structures. The trenches provide alternative current blocking paths through the insulating material filled within them, allowing the device to achieve high breakdown voltage without requiring large lateral diffused areas. This dimensional transition enables compact device footprint while maintaining high voltage capability.
3Area of stationary object
If substrate utilization is increased by reducing horizontal space, then area efficiency improves, but high voltage signal buffering may be compromised
Solution Approach 1:
The patent resolves this contradiction by moving the buffering function from the horizontal plane to the vertical dimension. The trench structures, extending downward to contact the buried layer, provide vertical pathways for voltage buffering and signal isolation. This allows compact horizontal layout with improved substrate utilization while maintaining adequate high voltage buffering through the vertical trench geometry and insulating material placement.
Data Source
AI summary
A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.