Trench Memory Device With Epitaxy Channel Length Control
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Solution Overview
Problem
Conventional memory devices face challenges in miniaturization, requiring a reduced substrate area for increased memory cell density while maintaining a sufficiently large surface area for charge storage, which is difficult to achieve with conventional trench capacitor structures.
Innovation Solution
The memory device features a trench with a collar dielectric layer and an epitaxy layer formed on both sides of the gate, allowing for precise control of the channel length and enlargement of the usable surface area, enhancing storage efficiency through a simpler trench top oxide formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional trench capacitor structures are used, then charge storage capability is maintained, but substrate area is too large for high-density memory cells
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical three-dimensional trench capacitors, utilizing the vertical dimension to increase storage capacitance without expanding substrate area. The trench capacitor extends vertically into the substrate, enabling higher charge storage density within the same footprint.
Solution Approach 2:
The patent implements a nested structure where the trench capacitor is formed within a vertical trench in the substrate. The collar dielectric layer is nested around the trench capacitor sidewalls, and the channel structure is nested within the trench region, creating a compact multi-layered configuration that maximizes space utilization.
2Productivity
If channel length is reduced to increase density, then memory cell density increases, but manufacturing precision becomes difficult to control
Solution Approach 1:
The collar dielectric layer serves as an intermediary structure that defines the channel region boundaries. By forming the collar dielectric layer around the trench capacitor sidewalls and using it as a reference for subsequent channel formation, the patent achieves precise channel length control through this intermediate structural element rather than direct dimensional control.
Solution Approach 2:
The patent performs preliminary formation of the collar dielectric layer and trench capacitor structure before defining the channel dimensions. This preliminary action establishes reference structures that guide subsequent channel formation, ensuring precise channel length control is achieved before final channel definition steps.
3Ease of manufacture
If trench aspect ratio is reduced to simplify TTO formation, then manufacturing complexity decreases, but usable surface area of trench decreases
Solution Approach 1:
The patent compensates for reduced trench surface area by utilizing the vertical dimension more effectively. The trench capacitor and collar dielectric layer are formed with optimized vertical dimensions, allowing adequate capacitance and functional area to be achieved through increased vertical extent rather than horizontal surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of the channel length to dimensions below 100 nm, increasing memory cell density and storage efficiency by enlarging the usable surface area within the trench, thus addressing the miniaturization challenges of conventional memory devices.
Implementation Method 1
an epitaxy layer formed on both sides of the gate and on the substrate
Data Source
AI summary
A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.