Trench Semiconductor Memory Device Channel Length Control
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Solution Overview
Problem
Conventional semiconductor-memory devices face challenges in reducing leak-off and controlling punch-through as cell size decreases, leading to increased channel length and impurity density issues, which affect ON current and threshold voltage stability.
Innovation Solution
The semiconductor-memory device incorporates a substrate with trench sections, selector gates, and floating gates, where the impurity density of the first well is less than the second well, allowing for a channel along the sidewall and bottom surface of the trench, effectively lengthening the channel and suppressing punch-through while maintaining impurity density control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell size is reduced to increase integration density, then productivity is improved, but leak-off increases and channel length control becomes difficult
Solution Approach 1:
The patent introduces a three-dimensional trench structure that extends vertically into the substrate, adding a depth dimension to the traditional planar cell layout. This vertical channel formation along the trench sidewalls allows for effective channel length control and leak-off suppression while maintaining reduced planar footprint, thus achieving high integration density without sacrificing reliability
2Productivity
If cell size is reduced to increase integration density, then productivity is improved, but channel length increases making punch-through control difficult
Solution Approach 1:
The trench structure creates a vertical channel path that separates the source and drain regions in the depth direction. This three-dimensional configuration allows the channel to extend vertically along the trench sidewall, providing sufficient effective channel length for punch-through control while the planar projection remains compact for high integration density
3Reliability
If impurity density is increased to suppress punch-through, then reliability is improved, but ON current decreases
Solution Approach 1:
The patent implements spatially varying impurity density distributions in different regions: higher impurity density in the channel region near the trench sidewall to suppress punch-through, and lower impurity density in the source/drain regions to maintain low resistance and high ON current. This localized optimization of impurity profiles resolves the contradiction between punch-through suppression and ON current maintenance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces leak-off, improves ON current, and stabilizes threshold voltage by creating a longer channel and optimizing impurity density distribution, enhancing the memory cell's performance even at smaller sizes.
Implementation Method 1
by utilizing tunneling between a floating gate and a control gate
Implementation Method 2
an inversion layer 220 is formed on the surface of the substrate below the selector gate 203 inside the cell area
Data Source
AI summary
A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1a; a first well 1b that is formed on the surface of the substrate 1 below the selector gate 3; a floating gate 6 that is located via an insulating film 8a on the surface of the bottom section and sidewall section of the trench section 1a; a second well 1c that is formed on the surface of the bottom section of the trench section 1a below the floating gate 6; a first diffusion area 7a that is formed on the surface of the bottom section of the trench section 1a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6; and where the area near the sidewall surface and bottom surface of the trench section 1a forms a channel in the selector gate 3; and the impurity density of the first well 1b is not more than the impurity density of the second well 1c.