Trench Memory Structure Preventing Punch Through
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Solution Overview
Problem
Conventional stack gate flash memory devices face issues with abnormal punch through due to reduced gate length and decreased gate coupling rate (GCR) as a result of miniaturization, affecting electrical performance and requiring higher operating voltages.
Innovation Solution
A memory structure is developed with a trench-based design, featuring a floating gate and control gate formed within a trench, utilizing a spacer and dielectric layers to increase channel length and prevent induced capacitance between adjacent floating gates, thereby enhancing electrical performance and GCR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to miniaturize memory cells, then the integration of memory devices is increased, but abnormal punch through between source and drain regions occurs and electrical performance deteriorates
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional trench-based gate structures. By etching trenches into the substrate and forming gates within these vertical structures, the invention extends the channel length in the vertical dimension while maintaining small lateral footprints. This dimensional transition allows miniaturization in the planar direction without sacrificing channel length, thereby preventing punch-through while achieving high integration.
Solution Approach 2:
The patent implements nested gate structures where a first gate is formed within a trench and a second gate is formed above it, creating a stacked configuration. This nesting approach allows multiple functional gates to occupy a compact vertical space, effectively increasing the channel length and improving electrical performance without increasing the lateral area, thus resolving the contradiction between miniaturization and reliability.
2Ease of manufacture
If two adjacent floating gates are isolated through a dielectric layer, then the structure follows conventional design, but induced capacitance is generated between adjacent floating gates and gate coupling rate is reduced
Solution Approach 1:
The patent extracts the problematic dielectric layer that isolates adjacent floating gates in conventional designs. By removing this insulating layer between vertically stacked gates, the invention enables direct electrical coupling between gates while maintaining structural integrity. This extraction eliminates the induced capacitance issue and restores high gate coupling rate, while the gates remain physically separated in the vertical dimension.
Data Source
AI summary
A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.