Self-Aligned Trench Memory Strap via Self-Limiting Recess
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Solution Overview
Problem
Existing methods face challenges in achieving precise and uniform recess depth of polysilicon within deep trenches across semiconductor wafers, due to variations in thickness, trench size, and recessing processes, which affects the formation of trench memory devices.
Innovation Solution
A self-aligned strap is formed using a self-limiting recess process in a semiconductor structure with a 'V' shape filling material, where the top portion is adjacent to the BOX layer, and a buried strap connects to the array transistor, ensuring uniformity and precision through a polysilicon spacer on the sidewall of the BOX layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional recessing processes are used to recess polysilicon in trenches, then the polysilicon can be recessed to a predetermined depth, but the recess depth varies across the wafer due to variations in polysilicon thickness, trench size, and recessing process
Solution Approach 1:
The polysilicon material serves itself as the etch stop layer. The recessing process automatically stops when it encounters the underlying layer, eliminating the need for external control mechanisms. This self-limiting recess ensures uniform depth across all trenches regardless of variations in polysilicon thickness or trench dimensions
Solution Approach 2:
The structure is designed in advance with the polysilicon filling extending beyond the BOX layer, creating an overhang. This preliminary configuration ensures that when recessing occurs, the polysilicon will naturally stop at the correct depth where it meets the BOX layer, preventing over-recessing and ensuring consistent electrical connections
2Reliability
If the polysilicon thickness is increased to ensure complete coverage, then the electrical connection is improved, but the recessing process becomes more difficult to control to a precise depth
Solution Approach 1:
The polysilicon material automatically regulates its own recessing depth by serving as the etch stop. The process stops when the polysilicon is recessed to the level of the BOX layer, eliminating the need for precise external control of recess depth while maintaining complete electrical coverage
Solution Approach 2:
The polysilicon is deposited to intentionally extend beyond the BOX layer in advance. This preliminary over-deposition ensures that even with variations in deposition thickness, the self-limiting recess process will always stop at the correct depth, providing both complete coverage and precise depth control
Data Source
AI summary
A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.