Trench MIS Tunneling Diode Structure for Stable Resistive Memory States
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Solution Overview
Problem
Existing semiconductor devices, particularly memory devices, face challenges in achieving stable and distinguishable resistive states for data storage due to insufficient current windows and unstable reverse bias currents, which affect memory performance.
Innovation Solution
The design of metal-insulator-semiconductor (MIS) tunneling diodes with edge trench structures that incorporate charge trapping sites at the trench edges, enhancing the reverse bias current and enlarging the memory window by controlling electron trapping and recombination processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device structures are used, then device simplicity is maintained, but current window is insufficient and reverse bias current is unstable
Solution Approach 1:
The device is segmented by introducing edge trenches that divide the semiconductor structure into distinct regions. These trenches create separate charge trapping sites at the edges, which stabilizes the reverse bias current by providing controlled pathways for charge carrier recombination, thereby improving the stability of resistive states without requiring complete structural redesign
Solution Approach 2:
Charge trapping sites are selectively introduced at the edge trench regions rather than uniformly throughout the device. This local modification creates specific zones with enhanced charge trapping capability, which stabilizes the reverse bias current and enlarges the memory window while maintaining the overall simplicity of the device structure
2Reliability
If charge trapping sites are added at trench edges, then current window is enlarged and memory performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The formation of charge trapping sites at the edge trenches is merged with the existing trench fabrication process. By integrating the charge trapping site creation into the trench formation step, the patent avoids adding separate manufacturing processes, thereby enlarging the current window and improving memory performance without significantly increasing fabrication complexity
Solution Approach 2:
Charge trapping sites are formed preliminarily during the trench fabrication process before final device assembly. This preliminary action ensures that the charge trapping sites are already in place to stabilize the reverse bias current and enlarge the memory window, while avoiding the need for additional post-fabrication processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trench-type MIS TD devices exhibit improved current windows and stable resistive states, enabling better differentiation between high and low resistive states for effective data storage, thus enhancing memory performance.
Implementation Method 1
a tunneling layer, 240, over the protruding portion 214
Implementation Method 2
incorporate charge trapping sites at the trench edges, enhancing the reverse bias current
Data Source
AI summary
An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.